New ADC V2 with Async support

Cargo.toml

@@ -1,12 +1,7 @@
 [workspace]
 resolver = "2"
 default-members = ["hal"]
-members = [
-	"hal",
-	"atsamd-hal-macros",
-	"pac/*",
-	"boards/*",
-]
+members = ["hal", "atsamd-hal-macros", "pac/*", "boards/*"]
 
 [profile.dev]
 debug = true

README.md

@@ -109,6 +109,7 @@ use the async APIs.
 * DMAC
 * EIC (GPIO interrupts)
 * Timers
+* ADC
 
 ### Examples
 

boards/feather_m0/Cargo.toml

@@ -87,6 +87,10 @@ required-features = ["adalogger", "usb", "sdmmc"]
 [[example]]
 name = "adc"
 
+[[example]]
+name = "async_adc"
+required-features = ["async"]
+
 [[example]]
 name = "async_dmac"
 required-features = ["dma", "async"]

boards/feather_m0/examples/adc.rs

@@ -1,41 +1,56 @@
 #![no_std]
 #![no_main]
 
+use atsamd_hal::adc::AdcBuilder;
+use feather_m0 as bsp;
+
+use bsp::hal;
+use bsp::pac;
+
 #[cfg(not(feature = "use_semihosting"))]
 use panic_halt as _;
 #[cfg(feature = "use_semihosting")]
 use panic_semihosting as _;
 
-use cortex_m_semihosting::hprintln;
-
-use bsp::hal;
-use bsp::pac;
-use feather_m0 as bsp;
-
 use bsp::entry;
-use hal::adc::Adc;
-use hal::clock::GenericClockController;
-use hal::prelude::*;
+use bsp::Pins;
 use pac::{CorePeripherals, Peripherals};
 
+use hal::{
+    adc::{Accumulation, Adc, Prescaler, Resolution},
+    clock::GenericClockController,
+};
+
 #[entry]
 fn main() -> ! {
     let mut peripherals = Peripherals::take().unwrap();
-    let core = CorePeripherals::take().unwrap();
+    let _core = CorePeripherals::take().unwrap();
+
+    let pins = Pins::new(peripherals.port);
+
+    // SAMD21 targets currently don't support clock::v2
     let mut clocks = GenericClockController::with_external_32kosc(
         peripherals.gclk,
         &mut peripherals.pm,
         &mut peripherals.sysctrl,
         &mut peripherals.nvmctrl,
     );
-    let pins = bsp::Pins::new(peripherals.port);
-    let mut delay = hal::delay::Delay::new(core.SYST, &mut clocks);
-    let mut adc = Adc::adc(peripherals.adc, &mut peripherals.pm, &mut clocks);
-    let mut a0: bsp::A0 = pins.a0.into();
+    let gclk0 = clocks.gclk0();
+    let adc_clock = clocks.adc(&gclk0).unwrap();
+
+    let mut adc = AdcBuilder::new(Accumulation::single(atsamd_hal::adc::AdcResolution::_12))
+        .with_clock_cycles_per_sample(5)
+        // Overruns if clock divider < 128 in debug mode
+        .with_clock_divider(Prescaler::Div128)
+        .with_vref(atsamd_hal::adc::Reference::Intvcc0)
+        .enable(peripherals.adc, &mut peripherals.pm, &adc_clock)
+        .unwrap();
+    let mut adc_pin = pins.a0.into_alternate();
 
     loop {
-        let data: u16 = adc.read(&mut a0).unwrap();
-        hprintln!("{}", data).ok();
-        delay.delay_ms(1000u16);
+        let mut _buffer = [0; 16];
+        adc.read_buffer(&mut adc_pin, &mut _buffer).unwrap();
+        #[cfg(feature = "use_semihosting")]
+        cortex_m_semihosting::hprintln!("Buffer: {:?}", _buffer).unwrap();
     }
 }

boards/feather_m0/examples/async_adc.rs

@@ -0,0 +1,61 @@
+#![no_std]
+#![no_main]
+
+use atsamd_hal::adc::AdcBuilder;
+use feather_m0 as bsp;
+
+use bsp::hal;
+use bsp::pac;
+
+#[cfg(not(feature = "use_semihosting"))]
+use panic_halt as _;
+#[cfg(feature = "use_semihosting")]
+use panic_semihosting as _;
+
+use bsp::Pins;
+use pac::{CorePeripherals, Peripherals};
+
+use hal::{
+    adc::{Accumulation, Adc, Adc0, Prescaler, Resolution},
+    clock::GenericClockController,
+};
+
+atsamd_hal::bind_interrupts!(struct Irqs {
+    ADC => atsamd_hal::adc::InterruptHandler<Adc0>;
+});
+
+#[embassy_executor::main]
+async fn main(_s: embassy_executor::Spawner) -> ! {
+    let mut peripherals = Peripherals::take().unwrap();
+    let _core = CorePeripherals::take().unwrap();
+
+    let pins = Pins::new(peripherals.port);
+
+    // SAMD21 targets currently don't support clock::v2
+    let mut clocks = GenericClockController::with_external_32kosc(
+        peripherals.gclk,
+        &mut peripherals.pm,
+        &mut peripherals.sysctrl,
+        &mut peripherals.nvmctrl,
+    );
+    let gclk0 = clocks.gclk0();
+    let adc_clock = clocks.adc(&gclk0).unwrap();
+
+    let mut adc = AdcBuilder::new(Accumulation::single(atsamd_hal::adc::AdcResolution::_12))
+        .with_clock_cycles_per_sample(5)
+        // Overruns if clock divider < 128 in debug mode
+        .with_clock_divider(Prescaler::Div128)
+        .with_vref(atsamd_hal::adc::Reference::Arefa)
+        .enable(peripherals.adc, &mut peripherals.pm, &adc_clock)
+        .unwrap()
+        .into_future(Irqs);
+
+    let mut adc_pin = pins.a0.into_alternate();
+
+    loop {
+        let mut _buffer = [0; 16];
+        adc.read_buffer(&mut adc_pin, &mut _buffer).await.unwrap();
+        #[cfg(feature = "use_semihosting")]
+        cortex_m_semihosting::hprintln!("Result: {:?}", &_buffer).unwrap();
+    }
+}

boards/feather_m4/Cargo.toml

@@ -35,6 +35,7 @@ version = "0.3.1"
 [dev-dependencies]
 heapless = "0.7"
 panic-halt = "0.2"
+cortex-m-semihosting = "0.5.0"
 panic-semihosting = "0.5"
 rtic = {version = "2.1.1", features = ["thumbv7-backend"]}
 smart-leds = "0.3"
@@ -53,6 +54,9 @@ usb = ["atsamd-hal/usb", "usb-device"]
 async = ["atsamd-hal/async"]
 use_semihosting = []
 
+[[example]]
+name = "adc"
+
 [[example]]
 name = "blinky_basic"
 

boards/feather_m4/examples/adc.rs

@@ -0,0 +1,60 @@
+#![no_std]
+#![no_main]
+
+use atsamd_hal::adc::AdcBuilder;
+use feather_m4 as bsp;
+
+use bsp::hal;
+use bsp::pac;
+
+#[cfg(not(feature = "use_semihosting"))]
+use panic_halt as _;
+#[cfg(feature = "use_semihosting")]
+use panic_semihosting as _;
+
+use bsp::entry;
+use bsp::Pins;
+use pac::{CorePeripherals, Peripherals};
+
+use hal::{
+    adc::{Accumulation, Adc, Prescaler, Resolution},
+    clock::v2::{clock_system_at_reset, pclk::Pclk},
+};
+
+#[entry]
+fn main() -> ! {
+    let mut peripherals = Peripherals::take().unwrap();
+    let _core = CorePeripherals::take().unwrap();
+
+    let pins = Pins::new(peripherals.port);
+
+    let (mut buses, clocks, tokens) = clock_system_at_reset(
+        peripherals.oscctrl,
+        peripherals.osc32kctrl,
+        peripherals.gclk,
+        peripherals.mclk,
+        &mut peripherals.nvmctrl,
+    );
+
+    // Enable the ADC0 ABP clock...
+    let apb_adc0 = buses.apb.enable(tokens.apbs.adc0);
+    // ...and enable the ADC0 PCLK. Both of these are required for the
+    // ADC to run.
+    let (pclk_adc0, _gclk0) = Pclk::enable(tokens.pclks.adc0, clocks.gclk0);
+
+    let mut adc = AdcBuilder::new(Accumulation::single(atsamd_hal::adc::AdcResolution::_12))
+        .with_clock_cycles_per_sample(5)
+        // Overruns if clock divider < 32 in debug mode
+        .with_clock_divider(Prescaler::Div32)
+        .with_vref(atsamd_hal::adc::Reference::Arefa)
+        .enable(peripherals.adc0, apb_adc0, &pclk_adc0)
+        .unwrap();
+    let mut adc_pin = pins.a0.into_alternate();
+
+    loop {
+        let mut _buffer = [0; 16];
+        adc.read_buffer(&mut adc_pin, &mut _buffer).unwrap();
+        #[cfg(feature = "use_semihosting")]
+        cortex_m_semihosting::hprintln!("Result: {:?}", &_buffer);
+    }
+}

boards/metro_m4/Cargo.toml

@@ -67,6 +67,10 @@ use_semihosting = []
 [[example]]
 name = "adc"
 
+[[example]]
+name = "async_adc"
+required-features = ["async"]
+
 [[example]]
 name = "async_dmac"
 required-features = ["dma", "async"]

boards/metro_m4/examples/adc.rs

@@ -1,6 +1,7 @@
 #![no_std]
 #![no_main]
 
+use atsamd_hal::adc::AdcBuilder;
 use metro_m4 as bsp;
 
 use bsp::hal;
@@ -11,35 +12,49 @@ use panic_halt as _;
 #[cfg(feature = "use_semihosting")]
 use panic_semihosting as _;
 
-use cortex_m_semihosting::hprintln;
-
 use bsp::entry;
-use hal::adc::Adc;
-use hal::clock::GenericClockController;
-use hal::gpio::B;
-use hal::prelude::*;
-use pac::gclk::pchctrl::Genselect::Gclk11;
+use bsp::Pins;
 use pac::{CorePeripherals, Peripherals};
 
+use hal::{
+    adc::{Accumulation, Adc, Prescaler, Resolution},
+    clock::v2::{clock_system_at_reset, pclk::Pclk},
+};
+
 #[entry]
 fn main() -> ! {
     let mut peripherals = Peripherals::take().unwrap();
-    let core = CorePeripherals::take().unwrap();
-    let mut clocks = GenericClockController::with_external_32kosc(
+    let _core = CorePeripherals::take().unwrap();
+
+    let pins = Pins::new(peripherals.port);
+
+    let (mut buses, clocks, tokens) = clock_system_at_reset(
+        peripherals.oscctrl,
+        peripherals.osc32kctrl,
         peripherals.gclk,
-        &mut peripherals.mclk,
-        &mut peripherals.osc32kctrl,
-        &mut peripherals.oscctrl,
+        peripherals.mclk,
         &mut peripherals.nvmctrl,
     );
-    let pins = bsp::Pins::new(peripherals.port);
-    let mut delay = hal::delay::Delay::new(core.SYST, &mut clocks);
-    let mut adc0 = Adc::adc0(peripherals.adc0, &mut peripherals.mclk, &mut clocks, Gclk11);
-    let mut a0 = pins.a0.into_alternate::<B>();
+
+    // Enable the ADC0 ABP clock...
+    let apb_adc0 = buses.apb.enable(tokens.apbs.adc0);
+    // ...and enable the ADC0 PCLK. Both of these are required for the
+    // ADC to run.
+    let (pclk_adc0, _gclk0) = Pclk::enable(tokens.pclks.adc0, clocks.gclk0);
+
+    let mut adc = AdcBuilder::new(Accumulation::single(atsamd_hal::adc::AdcResolution::_12))
+        .with_clock_cycles_per_sample(5)
+        // Overruns if clock divider < 32 in debug mode
+        .with_clock_divider(Prescaler::Div32)
+        .with_vref(atsamd_hal::adc::Reference::Arefa)
+        .enable(peripherals.adc0, apb_adc0, &pclk_adc0)
+        .unwrap();
+    let mut adc_pin = pins.a0.into_alternate();
 
     loop {
-        let data: u16 = adc0.read(&mut a0).unwrap();
-        hprintln!("{}", data).ok();
-        delay.delay_ms(1000u16);
+        let mut _buffer = [0; 16];
+        adc.read_buffer(&mut adc_pin, &mut _buffer).unwrap();
+        #[cfg(feature = "use_semihosting")]
+        cortex_m_semihosting::hprintln!("Result: {:?}", &_buffer).unwrap();
     }
 }