feat(tricore): Initial tricore support by miguelafsilva5 · Pull Request #242 · bao-project/bao-hypervisor

miguelafsilva5 · 2025-08-29T14:03:37Z

PR Description

This PR introduces the initial support for Infineon Tricore architectures.
This PR requires #218 to support boot from flash with a non-unified memory model.
The current state of this port supports baremetal and freeRTOS guests in single or multicore setups. At the moment, each guest is given an unique ID, and each core only executes one guest.

The following list shows what is missing:

DMA virtualization/isolation
History re-write and commit clean up
CI integration
bao-demos integration

DavidMCerdeira

This is just a quick review.
For now the my main comments are regarding stale code comments and magic numbers, I don't think my comments address them all, please check them more carefully than I did.
There's also some instances of using platformed defined values that need to be made more general to handle multiple platforms.

src/arch/tricore/inc/arch/cache.h

src/arch/tricore/inc/arch/fences.h

src/arch/tricore/inc/arch/hypercall.h

DavidMCerdeira · 2025-12-16T14:07:38Z

src/arch/tricore/inc/arch/interrupts.h

+#define IPI_CPU_MSG            (0x1460 / 4) /* TODO this is the first GPSR in TC49 */
+#define GSPR_SRC_BASE          (0x1460 / 4) /* TODO this is the first GPSR in TC49 */


Move to a platform defined

IPI_CPU_MSG needs to stay in this file due to other core files. The other is fixed in 62b4555

What's the problem with including platform.h for the correct IPI_CPU_MSG?
Otherwise this assumes all TC4 platforms have IPI_CPU_MSG in the same place

IR_MAX_INTERRUPTS and GSPR_SRC_BASE were moved to the wrong file

It was a distraction. Moved them to a wrong file. Should be fixed in 8620639

GSPR_SRC_BASE should be in src/platform/tc4dx/inc/plat/platform.h

src/arch/tricore/inc/arch/ir.h

src/arch/tricore/vm.c

src/platform/drivers/tricore_uart/tricore_uart.c

src/platform/tc4dx/platform.mk

Makefile

src/platform/tc4dx/tc4dx_desc.c

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

Optimizations were replacing calls with jump-links, which in turn were using more stack instead of CSAs. Increasing the stack size solved this problem. Furthermore, refactored the unlock function to include memory in the clobber list. Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

DavidMCerdeira

I've finished my second pass
In comments were I suggest to consider something, I believe it's worth doing but open to discuss why we shouldn't

DavidMCerdeira · 2026-02-13T10:24:17Z

src/arch/tricore/inc/arch/prot.h

+    accessen->WRA |= ACCESSEN_CPU0_MASK << (cpuid * 2);
+    accessen->RDA |= ACCESSEN_CPU0_MASK << (cpuid * 2);


It's better to create a macro that takes cpuid as an argument and outputs the correct mask.
Something like ACCESSEN_CPU_MASK(c)

DavidMCerdeira · 2026-02-13T10:25:43Z

src/arch/tricore/inc/arch/prot.h

+{
+    unsigned long temp = PROT_ODEF_MASK | PROT_OWEN_MASK;
+    temp |= (vm << PROT_VM_POS);
+    temp |= (cpu * 2 << PROT_TAGID_POS);


Again I suggest a macro that takes cpuid as an argument and outputs the correct bits

DavidMCerdeira · 2026-02-13T11:29:51Z

src/arch/tricore/mpu.c

+    bitmap_clear_consecutive(cpu()->arch.mpu.data_locked, 0, MPU_DATA_MAX_NUM_ENTRIES);
+
+    for (mpid_t mpid = 0; mpid < MPU_CODE_MAX_NUM_ENTRIES; mpid++) {
+        cpu()->arch.mpu.code_entries[mpid].mpid = mpid;


If mpid indexes the entry, why do we need to store mpid?

DavidMCerdeira · 2026-02-13T11:33:26Z

src/arch/tricore/mpu.c

+
+void mpu_enable(void)
+{
+    csfr_corecon_write(2);


magic number, should also it should only set the relevant bit

DavidMCerdeira · 2026-02-13T11:33:49Z

src/platform/tc4dx/platform.c

+        }
+
+        csfr_cpu_pc_write(coreid, load_addr);
+        csfr_cpu_bootcon_write(coreid, 0);


magic number

DavidMCerdeira · 2026-02-13T15:28:10Z

src/platform/tc4dx/tc4dx_desc.c

+const struct plat_device dev_array[] = {
+    {


Consider moving to seperate c module for the sake of readability

DavidMCerdeira · 2026-02-13T15:28:37Z

src/platform/tc4dx/tc4dx_desc.c

+#include <platform.h>
+
+#ifdef GENERATING_DEFS
+uint32_t plat_ints[] = { 0, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,


consider moving to its own module for the sake of readability

DavidMCerdeira · 2026-02-13T15:29:20Z

src/platform/tc4dx/tc4dx_desc.c

+            .int_addr = 0xF4430000,
+            .src_addr = 0xF4432000,
+            .GPSR_offset = 0x700,
+            .GPSR_size = (0xB00 + (8*4)) - 0x700,


magic numbers

DavidMCerdeira · 2026-02-13T15:30:06Z

src/platform/tc4dx/tc4dx_desc.c

+#ifdef MEM_NON_UNIFIED
+        {
+            .base = 0xA0000000,
+            .size = 0x400000,
+            .perms = MEM_RX,
+        },
+#endif


Why add one this region if memory is non-unified?

Currently, you can change the .mk file to have bao be either unified or non-unified. I can remove that, if it seems better to you.

DavidMCerdeira · 2026-02-13T15:30:37Z

src/platform/tc4dx/tc4dx_desc.c

+#ifndef MEM_NON_UNIFIED
+        {
+            // DLMU1
+            .base = 0x90080000,
+            .size =   0x80000,
+            .perms = MEM_RWX,
+        },
+#endif  


Why remove this region if memory is unified?

Currently, you can change the .mk file to have bao be either unified or non-unified. I can remove that, if it seems better to you.

miguelafsilva5 force-pushed the feat/tricore branch 2 times, most recently from f92535a to 57284c8 Compare September 1, 2025 14:05

danielRep force-pushed the feat/non-unified-mem branch from 9ad59e5 to 474545c Compare September 1, 2025 15:56

miguelafsilva5 force-pushed the feat/tricore branch 2 times, most recently from b9e1caf to 7da4f29 Compare September 3, 2025 12:51

danielRep force-pushed the feat/non-unified-mem branch 2 times, most recently from 829c219 to 61b37aa Compare September 3, 2025 13:06

miguelafsilva5 force-pushed the feat/tricore branch 4 times, most recently from 0e5ea75 to bf61453 Compare September 8, 2025 09:37

danielRep force-pushed the feat/tricore branch from bf61453 to 20a40db Compare September 8, 2025 10:03

danielRep force-pushed the feat/non-unified-mem branch 2 times, most recently from 674ffd5 to 3d1e91a Compare September 8, 2025 11:01

miguelafsilva5 force-pushed the feat/tricore branch from 20a40db to fd1cd5d Compare September 8, 2025 12:06

danielRep force-pushed the feat/non-unified-mem branch from 3d1e91a to 53e6ea9 Compare September 9, 2025 13:40

miguelafsilva5 force-pushed the feat/tricore branch 2 times, most recently from 44a2cbb to 3d6619f Compare September 10, 2025 10:18

danielRep force-pushed the feat/non-unified-mem branch from 04f6748 to 1a50d5c Compare September 10, 2025 11:00

miguelafsilva5 force-pushed the feat/tricore branch from 3d6619f to 1e889fb Compare September 10, 2025 11:03

Base automatically changed from feat/non-unified-mem to main September 10, 2025 13:32

miguelafsilva5 force-pushed the feat/tricore branch 6 times, most recently from bffccac to 661df87 Compare September 15, 2025 13:43

miguelafsilva5 force-pushed the feat/tricore branch 2 times, most recently from ba20ef7 to f2194f5 Compare September 24, 2025 10:31

miguelafsilva5 force-pushed the feat/tricore branch from f2194f5 to f245bf9 Compare October 2, 2025 14:50

miguelafsilva5 force-pushed the feat/tricore branch from 85e295e to 319dace Compare December 16, 2025 13:45

DavidMCerdeira requested changes Dec 16, 2025

View reviewed changes

miguelafsilva5 force-pushed the feat/tricore branch 2 times, most recently from 0878a8c to c3db84e Compare December 17, 2025 16:17

miguelafsilva5 force-pushed the feat/tricore branch from c3db84e to abd09d6 Compare January 9, 2026 15:31

miguelafsilva5 force-pushed the feat/tricore branch 2 times, most recently from 83500c2 to c5745c5 Compare January 19, 2026 16:36

miguelafsilva5 force-pushed the feat/tricore branch from c5745c5 to 860b5b8 Compare January 27, 2026 10:22

miguelafsilva5 force-pushed the feat/tricore branch from 860b5b8 to 1bc98b7 Compare February 10, 2026 15:04

feat(tricore): Initial commit

5cf813f

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

miguelafsilva5 force-pushed the feat/tricore branch from 1bc98b7 to 5cf813f Compare February 10, 2026 15:23

miguelafsilva5 added 2 commits February 10, 2026 15:57

ref(macros): Add macros to replace magic numbers

f5d2c67

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(platform): Move plat macros to a platform header

62b4555

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

miguelafsilva5 force-pushed the feat/tricore branch from e2a03e4 to 62b4555 Compare February 10, 2026 16:02

miguelafsilva5 added 4 commits February 12, 2026 14:37

ref(cache): uncomment a warning on flush

be27123

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(arch-idle): remove unused arch_idle function

c2376db

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(magic-num): Refactor magic numbers regarding GSPR

8a2cbcb

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

miguelafsilva5 force-pushed the feat/tricore branch from 81871e4 to 8a2cbcb Compare February 12, 2026 15:04

miguelafsilva5 added 4 commits February 12, 2026 15:16

ref(vm-irq): remove duplicated evaluation of irqs for vms

e0f44bb

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(literals): Refactor literal bools and magic number

4b713bd

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(regs): use memset to zero the arch_regs initial state

c803dc2

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(run): Added a comment on vcpu_arch_run

c2c9fcc

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

miguelafsilva5 force-pushed the feat/tricore branch from 5ae13a6 to c2c9fcc Compare February 12, 2026 16:05

miguelafsilva5 added 5 commits February 12, 2026 16:06

ref(uart): Change magic numbers to flag names

f214b22

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(plat-macros): moved macros to the correct file

8620639

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(vmen): changed ir icu vmen mask macro

6bf4c65

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

ref(arch-run): delete unused vpu_arch_run function

2e39a16

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

fix(powerdown_standby): implemented standby and powerdown functions

4709b14

Signed-off-by: Miguel Silva <miguelafsilva5@gmail.com>

DavidMCerdeira requested changes Feb 13, 2026

View reviewed changes

		#define IPI_CPU_MSG (0x1460 / 4) /* TODO this is the first GPSR in TC49 */
		#define GSPR_SRC_BASE (0x1460 / 4) /* TODO this is the first GPSR in TC49 */

		accessen->WRA \|= ACCESSEN_CPU0_MASK << (cpuid * 2);
		accessen->RDA \|= ACCESSEN_CPU0_MASK << (cpuid * 2);

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