Arm v8.2 #8
Arm v8.2 #8
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Thanks for the patch. |
lgeek
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lgeek
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Hi. I've reviewed the patch against ARM DDI 0487B.b, which I believe is the last ARMv8.2 architecture manual. See the inline comments for some requested changes. It would also be useful if you could rebase it on the git HEAD, as I've already merged the AArch32 changes.
I haven't checked the SVE instructions, I think it would be more appropriate to leave them out or move them to a different PR
| FMOV_immed 00011110 aa1bbbbb bbb10000 000ccccc, a:type, b:imm8, c:rd | ||
| float_cvt_fixed a0011110 bb0ccddd eeeeeeff fffggggg, a:sf, b:type, c:rmode, d:opcode, e:scale, f:rn, g:rd | ||
| float_cvt_int a0011110 bb1ccddd 000000ee eeefffff, a:sf, b:type, c:rmode, d:opcode, e:rn, f:rd | ||
| float_immed a0b11110 cc1ddddd ddd100ee eeefffff, a:m, b:s, c:ptype, d:imm8, e:imm5, f:rd |
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As far as I can see on page C4-321, all the allocated instructions covered by float_immed are already covered by FMOV_immed so I don't think float_immed is needed. Please double check this. In any case, we should only keep one of these 2 definitions.
| float_cvt_int a0011110 bb1ccddd 000000ee eeefffff, a:sf, b:type, c:rmode, d:opcode, e:rn, f:rd | ||
| float_immed a0b11110 cc1ddddd ddd100ee eeefffff, a:m, b:s, c:ptype, d:imm8, e:imm5, f:rd | ||
| float_cvt_fixed a0s11110 bb0ccddd eeeeeeff fffggggg, a:sf, s:s, b:type, c:rmode, d:opcode, e:scale, f:rn, g:rd | ||
| float_cvt_int a0s11110 bb1ccddd 000000ee eeefffff, a:sf, s:s, b:type, c:rmode, d:opcode, e:rn, f:rd |
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Same as above for float_cvt_fixed and float_cvt_int, it doesn't look like S(bit 29)=1 for any of the instructions defined in ARMv8.2 (page C4-311).
| float_immed a0b11110 cc1ddddd ddd100ee eeefffff, a:m, b:s, c:ptype, d:imm8, e:imm5, f:rd | ||
| float_cvt_fixed a0s11110 bb0ccddd eeeeeeff fffggggg, a:sf, s:s, b:type, c:rmode, d:opcode, e:scale, f:rn, g:rd | ||
| float_cvt_int a0s11110 bb1ccddd 000000ee eeefffff, a:sf, s:s, b:type, c:rmode, d:opcode, e:rn, f:rd | ||
| simd_three_reg_ext 0ab01110 cc0ddddd 1oooo1ee eeefffff, a:q, b:u, c:size, d:rm, e:rn, f:rd, o:opcode |
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This is 'Advanced SIMD three same extra (page C4-296)', right? The name should be updated to better match the documentation
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Encodings for ARM v8.2 instructions added.