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Support primitive gates with names in Verilog netlist #412

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Support primitive gates with names in Verilog netlist #412

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22 changes: 18 additions & 4 deletions src/base/ver/verCore.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1339,12 +1339,26 @@ int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t Ga
return 0;
Ver_StreamMove( p );

// this is gate name - throw it away
// assume there is a gate name if the current char is not '(', e.g. xor g1 (z, a, b);
if ( Ver_StreamPopChar(p) != '(' )
{
sprintf( pMan->sError, "Cannot parse a standard gate (expected opening parenthesis)." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
// this is gate name - throw it away
pWord = Ver_ParseGetName( pMan );
if (pWord == NULL)
{
sprintf( pMan->sError, "Cannot parse a standard gate (expected a name before an opening parenthesis)." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
else
{
if ( Ver_StreamPopChar(p) != '(' )
{
sprintf( pMan->sError, "Cannot parse a standard gate (expected opening parenthesis)." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
}
}
Ver_ParseSkipComments( pMan );

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