WIP: Create a backwards compatible flow for xo/xclbin generation with Calyx-AXI-wrapper

fud/fud/xclrun.py

@@ -86,12 +86,8 @@ def run(xclbin: Path, data: Mapping[str, Any]) -> Dict[str, Any]:
         buffer.sync_to_device()
 
     # Run the kernel.
-    kernel = getattr(ol, list(ol.ip_dict)[0])  # Like ol.Toplevel_1
-    # XXX(nathanielnrn) 2022-07-19: timeout is not currently used anywhere in
-    # generated verilog code, passed in because kernel.xml is generated to
-    # expect it as an argument
-    timeout = 1000
-    kernel.call(timeout, *buffers)
+    kernel = getattr(ol, list(ol.ip_dict)[0])  # Like ol.wrapper_1
+    kernel.call(*buffers)
 
     # Collect the output data.
     for buf in buffers:

fud2/scripts/calyx.rhai

@@ -17,6 +17,7 @@ fn calyx_setup(e) {
        "calyx-cider",
        "$calyx-exe -l $calyx-lib-path $cider-calyx-passes $args $in > $out",
    );
+   e.rule("copy", "cp $in $out");
 }
 
 op(

fud2/scripts/cocotb-axi.rhai

@@ -26,7 +26,7 @@ fn cocotb_setup(e) {
     e.rule("copy", "cp $in $out");
     // This cleans up the extra `make` cruft, leaving what is in between `{` and `}.`
     e.rule(
-      "cleanup-cocotb", `sed -n '/Output:/,/make\[1\]/{/Output:/d;/make\[1\]/d;p}' $in > $out`
+      "cleanup-cocotb", `sed -n '/Output:/,/make\[1\]/{/Output:/d;/make\[1\]/d;p;}' $in > $out`
     );
 }
 
@@ -49,6 +49,8 @@ op(
     c::verilog_noverify,
     cocotb_axi,
     |e, input, output| {
+        // Cocotb wants files relative to the location of the makefile.
+        // This is annoying to calculate on the fly, so we just copy necessary files to the build directory
         e.build_cmd(
             ["Makefile"],
             "copy",

fud2/scripts/xilinx.rhai

@@ -1,10 +1,14 @@
-import "calyx" as c;
+// import "calyx" as c;
+import "axi" as axi;
 import "rtl_sim" as sim;
 import "testbench" as tb;
 
 let xo = state("xo", ["xo"]);
 let xclbin = state("xclbin", ["xclbin"]);
 
+fn default_xml_generator() {
+    "$calyx-base/yxi/xml/xml_generator.py";
+}
 fn xilinx_setup(e) {
     // Locations for Vivado and Vitis installations.
     e.config_var("vivado-dir", "xilinx.vivado");
@@ -28,12 +32,16 @@ fn xilinx_setup(e) {
         "$vitis-dir/bin/v++ -g -t $xilinx-mode --platform $platform --save-temps --profile.data all:all:all --profile.exec all:all:all -lo $out $in"
     );
     e.arg("pool", "console");
+
+    // Generate a kernel.xml from a yxi file.
+    e.config_var_or("xml-generator", "xml.generator", default_xml_generator());
+    e.rule("gen-kernel-xml", "$python $xml-generator $in > $out");
 };
 
 op(
     "xo",
-    [c::calyx_setup, xilinx_setup],
-    c::calyx_state,
+    [axi::c::calyx_setup, xilinx_setup],
+    axi::c::calyx_state,
     xo,
     |e, input, output| {
         // Emit the Verilog itself in "synthesis mode."
@@ -60,7 +68,50 @@ op(
                "get-ports.py",
             ],
         );
-    },
+    }
+);
+
+// Assumes that verilog was generated with the `--synthesis` flag.
+// `-p external` can also be used, but is not necesary for designs using `ref` memories.
+op(
+    "verilog-to-xo",
+    [axi::c::calyx_setup, xilinx_setup],
+    axi::c::verilog_state,
+    xo,
+    |e, input, output | {
+        let file_name = input.split("/")[-1];
+        let sv_file_name = file_name;
+        sv_file_name.replace(`v`, `sv`);
+        let yxi_file = e.config_val("yxi.file");
+        let yxi_path = e.external_path(yxi_file);
+
+        e.build_cmd(
+            ["kernel.xml"],
+            "gen-kernel-xml",
+            [yxi_path],
+            ["$xml-generator"],
+        );
+
+        e.build_cmd(
+            [sv_file_name],
+            "copy",
+            [input],
+            [],
+        );
+
+        e.build_cmd(
+            [output],
+            "gen-xo",
+            [], 
+            [
+                sv_file_name,
+                yxi_path,
+                "gen_xo.tcl",
+                "get-ports.py",
+                "kernel.xml",
+            ],
+        );
+    }
 );
 
 op("xclbin", [xilinx_setup], xo, xclbin, |e, input, output| {

fud2/tests/snapshots/tests__test@plan_calyx-to-cocotb-axi.snap

@@ -26,7 +26,7 @@ rule make-cocotb
 rule copy
   command = cp $in $out
 rule cleanup-cocotb
-  command = sed -n '/Output:/,/make\[1\]/{/Output:/d;/make\[1\]/d;p}' $in > $out
+  command = sed -n '/Output:/,/make\[1\]/{/Output:/d;/make\[1\]/d;p;}' $in > $out
 
 build Makefile: copy $cocotb-makefile-dir/Makefile
 build axi_test.py: copy $cocotb-makefile-dir/axi_test.py