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Merged
sampsyo merged 5 commits into from
Jul 31, 2025
Merged

[repo] Bump rust version and dependencies #2532

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9912721
bump rust version
EclecticGriffin Jul 29, 2025
d043065
bump all the versions so dependabot shuts up
EclecticGriffin Jul 29, 2025
cc7d7e9
resolve warning
EclecticGriffin Jul 29, 2025
fb2646b
clippy is real mad
EclecticGriffin Jul 29, 2025
6d0e6dd
formatting
EclecticGriffin Jul 29, 2025
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1,106 changes: 624 additions & 482 deletions Cargo.lock
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2 changes: 1 addition & 1 deletion Cargo.toml
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Expand Up @@ -45,7 +45,7 @@ categories = ["compilers"]
homepage = "https://calyxir.org"
edition = "2024"
version = "0.7.1"
rust-version = "1.85"
rust-version = "1.88"

[workspace.dependencies]
# Internal crates
Expand Down
2 changes: 1 addition & 1 deletion benches/component-sharing.rs
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Expand Up @@ -17,7 +17,7 @@ fn cell_share_bench(c: &mut Criterion) {
b.iter_batched(
|| {
let name =
format!("benches/component-sharing/{}.futil", name);
format!("benches/component-sharing/{name}.futil");
let bench = Path::new(&name);
let lib = [PathBuf::from(".")];

Expand Down
3 changes: 1 addition & 2 deletions calyx/backend/src/backend_opt.rs
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Expand Up @@ -54,8 +54,7 @@ impl FromStr for BackendOpt {
.map(|(name, _)| (*name).to_string())
.join(", ");
Err(format!(
"`{}` is not a valid backend.\nValid backends: {}",
input, backend_str
"`{input}` is not a valid backend.\nValid backends: {backend_str}"
))
}
}
Expand Down
12 changes: 6 additions & 6 deletions calyx/backend/src/firrtl.rs
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Expand Up @@ -185,7 +185,7 @@ fn emit_primitive_extmodule<F: io::Write>(
param_binding: &Binding,
f: &mut F,
) -> io::Result<()> {
writeln!(f, "{}extmodule {}:", SPACING, curr_module_name)?;
writeln!(f, "{SPACING}extmodule {curr_module_name}:")?;
for port in ports {
let port_borrowed = port.borrow();
emit_port(port_borrowed, false, f)?;
Expand Down Expand Up @@ -251,16 +251,16 @@ fn get_guard_string(guard: &ir::Guard<ir::Nothing>) -> String {
ir::Guard::Or(l, r) => {
let l_str = get_guard_string(l.as_ref());
let r_str = get_guard_string(r.as_ref());
format!("or({}, {})", l_str, r_str)
format!("or({l_str}, {r_str})")
}
ir::Guard::And(l, r) => {
let l_str = get_guard_string(l.as_ref());
let r_str = get_guard_string(r.as_ref());
format!("and({}, {})", l_str, r_str)
format!("and({l_str}, {r_str})")
}
ir::Guard::Not(g) => {
let g_str = get_guard_string(g);
format!("not({})", g_str)
format!("not({g_str})")
}
ir::Guard::True => String::from(""),
ir::Guard::CompOp(op, l, r) => {
Expand All @@ -274,7 +274,7 @@ fn get_guard_string(guard: &ir::Guard<ir::Nothing>) -> String {
ir::PortComp::Geq => "geq",
ir::PortComp::Leq => "leq",
};
format!("{}({}, {})", op_str, l_str, r_str)
format!("{op_str}({l_str}, {r_str})")
}
ir::Guard::Port(port) => get_port_string(&port.borrow(), false),
ir::Guard::Info(_) => {
Expand All @@ -293,7 +293,7 @@ fn get_port_string(port: &calyx_ir::Port, is_dst: bool) -> String {
match parent.prototype {
ir::CellType::Constant { val, width: _ } => {
if !is_dst {
format!("UInt({})", val)
format!("UInt({val})")
} else {
unreachable!()
}
Expand Down
4 changes: 2 additions & 2 deletions calyx/backend/src/mlir.rs
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Expand Up @@ -229,7 +229,7 @@ impl MlirBackend {
.map(|p| format!("%{}.{}", name, p.borrow().name))
.collect::<Vec<_>>()
.join(", ");
write!(f, "{} = ", all_ports)?;
write!(f, "{all_ports} = ")?;
let supports_attrs =
Self::write_prototype_sig(&cell.prototype, name.as_str(), f)?;
if supports_attrs {
Expand All @@ -242,7 +242,7 @@ impl MlirBackend {
.map(|p| format!("i{}", p.borrow().width))
.collect::<Vec<_>>()
.join(", ");
writeln!(f, "{}", all_port_widths)
writeln!(f, "{all_port_widths}")
}

/// Format and write an assignment.
Expand Down
9 changes: 3 additions & 6 deletions calyx/backend/src/resources.rs
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Expand Up @@ -135,7 +135,7 @@ fn estimated_size(count_map: HashMap<(ir::Id, ir::Binding, bool), u32>) {
};
let externalize_name = |name: ir::Id, is_external: bool| {
if is_external {
format!("external {}", name)
format!("external {name}")
} else {
name.to_string()
}
Expand Down Expand Up @@ -275,9 +275,6 @@ fn estimated_size(count_map: HashMap<(ir::Id, ir::Binding, bool), u32>) {
_ => (),
}
}
eprintln!("Estimated size in bit(s): {}", estimated_size);
eprintln!(
"Estimated external size in bit(s): {}",
estimated_external_size
);
eprintln!("Estimated size in bit(s): {estimated_size}");
eprintln!("Estimated external size in bit(s): {estimated_external_size}");
}
46 changes: 18 additions & 28 deletions calyx/backend/src/verilog.rs
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Expand Up @@ -124,16 +124,14 @@ trait LibraryHandlerTrait {
for dir in library_dirs {
let entries = std::fs::read_dir(&dir).map_err(|e| {
Error::invalid_file(format!(
"Error accessing library directory `{:?}`: {}",
dir, e
"Error accessing library directory `{dir:?}`: {e}"
))
})?;

for entry in entries {
let entry = entry.map_err(|e| {
Error::invalid_file(format!(
"Error reading entry in directory `{:?}`: {}",
dir, e
"Error reading entry in directory `{dir:?}`: {e}"
))
})?;
library_paths.push(entry.path());
Expand Down Expand Up @@ -419,8 +417,7 @@ impl Backend for VerilogBackend {
morty::build_syntax_tree(&file_list, false, false, true, false)
.map_err(|err| {
Error::write_error(format!(
"Failed to build syntax tree with Morty: {}",
err
"Failed to build syntax tree with Morty: {err}"
))
})?;
let top_module = ctx.entrypoint.to_string();
Expand All @@ -437,7 +434,7 @@ impl Backend for VerilogBackend {
true,
false,
)
.map_err(|err| Error::write_error(format!("{}", err)))?;
.map_err(|err| Error::write_error(format!("{err}")))?;
}
// Rewind to the start of the temporary file so that we can read the content
temp_writer.seek(SeekFrom::Start(0)).map_err(|_| {
Expand All @@ -454,12 +451,7 @@ impl Backend for VerilogBackend {
let mut final_writer = file.get_write();
final_writer
.write_all(temp_content.as_bytes())
.map_err(|err| {
io::Error::new(
io::ErrorKind::Other,
format!("Write failed: {}", err),
)
})?;
.map_err(|err| io::Error::other(format!("Write failed: {err}")))?;
Ok(())
}
}
Expand All @@ -474,7 +466,7 @@ fn emit_prim_inline<F: io::Write>(
if !prim.params.is_empty() {
writeln!(f, " #(")?;
for (idx, param) in prim.params.iter().enumerate() {
write!(f, " parameter {} = 32", param)?;
write!(f, " parameter {param} = 32")?;
if idx != prim.params.len() - 1 {
writeln!(f, ",")?;
} else {
Expand Down Expand Up @@ -582,7 +574,7 @@ fn emit_component<F: io::Write>(
if !synthesis_mode {
memory_read_write(comp)
.into_iter()
.try_for_each(|stmt| writeln!(f, "{}", stmt))?;
.try_for_each(|stmt| writeln!(f, "{stmt}"))?;
}

let cells = comp
Expand All @@ -593,7 +585,7 @@ fn emit_component<F: io::Write>(
// structure wire declarations
cells.iter().try_for_each(|(name, width, _)| {
let decl = v::Decl::new_logic(name, *width);
writeln!(f, "{};", decl)
writeln!(f, "{decl};")
})?;

// cell instances
Expand Down Expand Up @@ -740,9 +732,7 @@ fn cell_instance(cell: &ir::Cell) -> Option<v::Instance> {
param_binding.iter().for_each(|(name, value)| {
if *value > (i32::MAX as u64) {
panic!(
"Parameter value {} for `{}` cannot be represented using 32 bits",
value,
name
"Parameter value {value} for `{name}` cannot be represented using 32 bits"
)
}
inst.add_param(
Expand Down Expand Up @@ -835,7 +825,7 @@ fn emit_fsms<F: io::Write>(
collection.into_iter().enumerate()
{
// string representing the new guard on the assignment
let case_guard = format!("{}_s{state}_out", fsm_id);
let case_guard = format!("{fsm_id}_s{state}_out");
let case_guarded_assign_guard = if assignment.guard.is_true() {
case_guard
} else {
Expand Down Expand Up @@ -936,12 +926,12 @@ fn emit_fsm_module<F: io::Write>(
if (reset) begin\n state_reg <= s0;\n end\n\
else begin\n state_reg <= state_next;\n\
end\n end\n";
writeln!(f, "{}", always_comb_header)?;
writeln!(f, "{always_comb_header}")?;

// Begin emitting the FSM's transitions and updates
let case_header = " always @(*) begin\n state_next = s0;\n\
case ( state_reg )";
writeln!(f, "{}", case_header)?;
writeln!(f, "{case_header}")?;
// At each state, write the updates to the state and the outward-facing
// wires to make high / low
for (case, trans) in fsm.borrow().transitions.iter().enumerate() {
Expand All @@ -966,7 +956,7 @@ fn emit_fsm_module<F: io::Write>(
// Wrap up the module
let case_footer = " endcase\n end\n\
endmodule\n";
writeln!(f, "{}", case_footer)?;
writeln!(f, "{case_footer}")?;

io::Result::Ok(())
}
Expand Down Expand Up @@ -1033,7 +1023,7 @@ fn emit_guard_disjoint_check(

// Generated error message
let ir::Canonical { cell, port } = dst.borrow().canonical();
let msg = format!("Multiple assignment to port `{}.{}'.", cell, port);
let msg = format!("Multiple assignment to port `{cell}.{port}'.");
let err = v::Sequential::new_seqexpr(v::Expr::new_call(
"$fatal",
vec![v::Expr::new_int(2), v::Expr::Str(msg)],
Expand Down Expand Up @@ -1429,11 +1419,11 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
vec![
v::Expr::Concat(v::ExprConcat {
exprs: vec![
v::Expr::new_str(&format!("/{}.dat", name)),
v::Expr::new_str(&format!("/{name}.dat")),
v::Expr::new_ref("DATA"),
],
}),
v::Expr::new_ipath(&format!("{}.{}", name, mem_access_str)),
v::Expr::new_ipath(&format!("{name}.{mem_access_str}")),
],
)));
});
Expand All @@ -1447,11 +1437,11 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
vec![
v::Expr::Concat(v::ExprConcat {
exprs: vec![
v::Expr::new_str(&format!("/{}.out", name)),
v::Expr::new_str(&format!("/{name}.out")),
v::Expr::new_ref("DATA"),
],
}),
v::Expr::new_ipath(&format!("{}.{}", name, mem_access_str)),
v::Expr::new_ipath(&format!("{name}.{mem_access_str}")),
],
)));
});
Expand Down
22 changes: 11 additions & 11 deletions calyx/backend/src/xilinx/control_axi.rs
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Expand Up @@ -80,13 +80,13 @@ impl ControlInterface for AxiInterface {
) -> Self {
// read channels
let read_address = AxiChannel {
prefix: format!("{}AR", prefix),
prefix: format!("{prefix}AR"),
direction: ChannelDirection::Recv,
state: vec![v::Decl::new_wire("raddr", address_width)],
data_ports: vec![("ADDR".to_string(), address_width)],
};
let read_data = AxiChannel {
prefix: format!("{}R", prefix),
prefix: format!("{prefix}R"),
direction: ChannelDirection::Send,
state: vec![v::Decl::new_reg("rdata", data_width)],
data_ports: vec![
Expand All @@ -97,19 +97,19 @@ impl ControlInterface for AxiInterface {

// write channels
let write_address = AxiChannel {
prefix: format!("{}AW", prefix),
prefix: format!("{prefix}AW"),
direction: ChannelDirection::Recv,
state: vec![v::Decl::new_reg("waddr", address_width)],
data_ports: vec![("ADDR".to_string(), address_width)],
};
let write_data = AxiChannel {
prefix: format!("{}W", prefix),
prefix: format!("{prefix}W"),
direction: ChannelDirection::Recv,
state: vec![v::Decl::new_wire("wdata", data_width)],
data_ports: vec![("DATA".to_string(), data_width)],
};
let write_response = AxiChannel {
prefix: format!("{}B", prefix),
prefix: format!("{prefix}B"),
direction: ChannelDirection::Send,
state: vec![],
data_ports: vec![("RESP".to_string(), 2)],
Expand Down Expand Up @@ -146,9 +146,9 @@ impl ControlInterface for AxiInterface {
vec![(0..32, "int_timeout", 0..32, Flags::default().write())],
);
for (idx, memory_name) in memories.iter().enumerate() {
let part0_name = format!("{}_0", memory_name);
let part1_name = format!("{}_1", memory_name);
let addr_name = format!("addr_{}", memory_name);
let part0_name = format!("{memory_name}_0");
let part1_name = format!("{memory_name}_1");
let addr_name = format!("addr_{memory_name}");
addr_space.add_address(
0x18 + (idx * 8),
&part0_name,
Expand Down Expand Up @@ -257,9 +257,9 @@ impl ControlInterface for AxiInterface {
);

for memory in memories {
let part0_name = format!("{}_0", memory);
let part1_name = format!("{}_1", memory);
let addr_name = format!("addr_{}", memory);
let part0_name = format!("{memory}_0");
let part1_name = format!("{memory}_1");
let addr_name = format!("addr_{memory}");
module.add_stmt(v::Parallel::Assign(
memory.as_str().into(),
addr_name.into(),
Expand Down
12 changes: 6 additions & 6 deletions calyx/backend/src/xilinx/memory_axi.rs
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Expand Up @@ -39,13 +39,13 @@ impl MemoryInterface for AxiInterface {
];
// read channels
let read_address = AxiChannel {
prefix: format!("{}AR", prefix),
prefix: format!("{prefix}AR"),
direction: ChannelDirection::Send,
state: vec![],
data_ports: addr_data_ports.clone(),
};
let read_data = AxiChannel {
prefix: format!("{}R", prefix),
prefix: format!("{prefix}R"),
direction: ChannelDirection::Recv,
state: vec![],
data_ports: vec![
Expand All @@ -58,13 +58,13 @@ impl MemoryInterface for AxiInterface {

// write channels
let write_address = AxiChannel {
prefix: format!("{}AW", prefix),
prefix: format!("{prefix}AW"),
direction: ChannelDirection::Send,
state: vec![],
data_ports: addr_data_ports,
};
let write_data = AxiChannel {
prefix: format!("{}W", prefix),
prefix: format!("{prefix}W"),
direction: ChannelDirection::Send,
state: vec![],
data_ports: vec![
Expand All @@ -75,7 +75,7 @@ impl MemoryInterface for AxiInterface {
],
};
let write_response = AxiChannel {
prefix: format!("{}B", prefix),
prefix: format!("{prefix}B"),
direction: ChannelDirection::Recv,
state: vec![],
data_ports: vec![
Expand Down Expand Up @@ -342,7 +342,7 @@ fn bram_logic(
let suffix_idx = "Memory_controller_axi_".len();
let suffix = &name[suffix_idx..];
let mut ram_instance =
v::Instance::new("bram", &format!("SINGLE_PORT_BRAM_{}", suffix));
v::Instance::new("bram", &format!("SINGLE_PORT_BRAM_{suffix}"));
ram_instance.connect_ref("ACLK", "ACLK");
ram_instance.connect_ref("ADDR", "bram_addr");
ram_instance.connect_ref("Din", "bram_write_data");
Expand Down
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