riscv: propagate register-class decode failure in custom decoders

[jmestwa-coder]

Your checklist for this pull request

• I've documented or updated the documentation of every API function and struct this PR changes.
• I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

Several hand-written RISC-V decoders drop the status of Decode*RegisterClass:

• decodeRegReg, decodeRVCInstrRdRs2, decodeRVCInstrRdRs1Rs2, decodeXTHeadMemPair and decodeRVCInstrRdRs1ImmZero call it and ignore the return
• in RVE mode a general register >= 16 is rejected (also reachable through the COREV and XThead paths), so the operand is never created but the decoder still returns success
• the printer then reads the missing operand: printRegReg passes a NULL register name to SStream_concat0, which is a NULL deref in release builds; printOperand reads a slot of unknown kind for the compressed and XThead forms
• the generated table decoders already guard the same calls with Check()

Return MCDisassembler_Fail when the register-class decode fails, at each site.

Test plan

• cstool -d riscv32+e+corev 2b330a2a (COREV cv.sh) faults on a NULL register name before the fix; after it, the word is rejected
• added test_riscv_rve_unchecked_reg_decode to tests/integration/test_poc.c, one input per fixed decoder, run under the ASAN/UBSan job
• added the rejected words to tests/issues/fuzzing.yaml
• ctest --test-dir build is green

Closing issues