Highlights
RISC-V
This release contains the highly awaited RISC-V module update.
Because RISC-V is in such active development the changes compared to the old module are enormous.
Please check out the RISC-V summary in the release guide for an overview.
We expect it to have some bugs so we are grateful for reports!
Capstone 32 bit builds
Capstone is now build and tested on several 32 bit architectures, including i686 Windows.
Consistent error reporting of CS_ERR_MEM
Fix possible NULL-pointer dereferences for out of memory events.
Capstone's API will now always return CS_ERR_MEM if allocations fail.
x86-64: Decoding of conflicting segment overrides was changed to match CPU behavior.
Please see the x86-64 section in the release guide for details.
What's Changed
- Refactoring the RISCV architecture to Auto-Sync on LLVM by @moste00 in #2756
- Added RISCV v6 release notes by @moste00 in #2846
- Package build workflow fix by @Rot127 in #2849
- Ignore ES/CS/SS/DS segment overrides in x64 mode by @jxors in #2819
- x86: fix decoding of mandatory prefixes by @jxors in #2856
- Fix unchecked allocations by @Grond66 in #2844
- Convert all README's to markdown files. by @Rot127 in #2863
- Fix 32bit build by @Rot127 in #2796
New Contributors
Full Changelog: 6.0.0-Alpha6...6.0.0-Alpha7
