rs, sys: bump capstone to 5.0.6

capstone-rs/src/arch/arm.rs

@@ -349,6 +349,7 @@ mod test {
             cc: arm_cc::ARM_CC_INVALID,
             update_flags: false,
             writeback: false,
+            post_index: false,
             mem_barrier: arm_mem_barrier::ARM_MB_INVALID,
             op_count: 0,
             operands: [

capstone-rs/src/arch/arm64.rs

@@ -5,7 +5,7 @@ use libc::c_uint;
 pub use crate::arch::arch_builder::arm64::*;
 use crate::arch::DetailsArchInsn;
 use crate::instruction::{RegId, RegIdInt};
-use capstone_sys::{arm64_op_mem, arm64_op_type, cs_arm64, cs_arm64_op};
+use capstone_sys::{arm64_op_mem, arm64_op_sme_index, arm64_op_type, cs_arm64, cs_arm64_op};
 use core::convert::From;
 use core::{cmp, fmt, mem, slice};
 
@@ -19,6 +19,7 @@ pub use capstone_sys::arm64_insn_group as Arm64InsnGroup;
 pub use capstone_sys::arm64_prefetch_op as ArmPrefetchOp;
 pub use capstone_sys::arm64_pstate as Arm64Pstate;
 pub use capstone_sys::arm64_reg as Arm64Reg;
+pub use capstone_sys::arm64_svcr_op as Arm64SvcrOp;
 pub use capstone_sys::arm64_sys_op as Arm64SysOp;
 pub use capstone_sys::arm64_sysreg as Arm64Sysreg;
 pub use capstone_sys::arm64_vas as Arm64Vas;
@@ -51,7 +52,11 @@ pub enum Arm64Shift {
 }
 
 impl Arm64OperandType {
-    fn new(op_type: arm64_op_type, value: cs_arm64_op__bindgen_ty_2) -> Arm64OperandType {
+    fn new(
+        op_type: arm64_op_type,
+        value: cs_arm64_op__bindgen_ty_2,
+        svcr: Arm64SvcrOp,
+    ) -> Arm64OperandType {
         use self::arm64_op_type::*;
         use self::Arm64OperandType::*;
 
@@ -72,6 +77,8 @@ impl Arm64OperandType {
             ARM64_OP_SYS => Sys(unsafe { value.sys }),
             ARM64_OP_PREFETCH => Prefetch(unsafe { value.prefetch }),
             ARM64_OP_BARRIER => Barrier(unsafe { value.barrier }),
+            ARM64_OP_SVCR => SVCR(svcr),
+            ARM64_OP_SME_INDEX => SMEIndex(Arm64OpSmeIndex(unsafe { value.sme_index })),
         }
     }
 }
@@ -131,6 +138,12 @@ pub enum Arm64OperandType {
     /// Memory barrier operation (ISB/DMB/DSB instructions)
     Barrier(Arm64BarrierOp),
 
+    /// SMSTART/SMSTOP mode (Streaming SVE & ZA storage)
+    SVCR(Arm64SvcrOp),
+
+    /// SME index
+    SMEIndex(Arm64OpSmeIndex),
+
     /// Invalid
     Invalid,
 }
@@ -183,6 +196,31 @@ impl_PartialEq_repr_fields!(Arm64OpMem;
 
 impl cmp::Eq for Arm64OpMem {}
 
+/// ARM64 sme index operand
+#[derive(Debug, Copy, Clone)]
+pub struct Arm64OpSmeIndex(pub(crate) arm64_op_sme_index);
+
+impl Arm64OpSmeIndex {
+    /// Register being indexed
+    pub fn reg(&self) -> RegId {
+        RegId(self.0.reg as RegIdInt)
+    }
+
+    /// Base register
+    pub fn base(&self) -> RegId {
+        RegId(self.0.base as RegIdInt)
+    }
+
+    /// Disp value
+    pub fn disp(&self) -> i32 {
+        self.0.disp as i32
+    }
+}
+
+impl_PartialEq_repr_fields!(Arm64OpSmeIndex;
+    reg, base, disp
+);
+
 impl Default for Arm64Operand {
     fn default() -> Self {
         Arm64Operand {
@@ -227,7 +265,7 @@ impl Arm64Shift {
 impl From<&cs_arm64_op> for Arm64Operand {
     fn from(op: &cs_arm64_op) -> Arm64Operand {
         let shift = Arm64Shift::new(op.shift.type_, op.shift.value);
-        let op_type = Arm64OperandType::new(op.type_, op.__bindgen_anon_1);
+        let op_type = Arm64OperandType::new(op.type_, op.__bindgen_anon_1, op.svcr);
         let vector_index = if op.vector_index >= 0 {
             Some(op.vector_index as u32)
         } else {
@@ -279,27 +317,40 @@ mod test {
         use super::Arm64Sysreg::*;
         use capstone_sys::arm64_prefetch_op::*;
         use capstone_sys::arm64_pstate::*;
+        use capstone_sys::arm64_svcr_op::*;
         use capstone_sys::*;
 
         fn t(
-            op_type_value: (arm64_op_type, cs_arm64_op__bindgen_ty_2),
+            op_type_value: (arm64_op_type, cs_arm64_op__bindgen_ty_2, arm64_svcr_op),
             expected_op_type: Arm64OperandType,
         ) {
-            let (op_type, op_value) = op_type_value;
-            let op_type = Arm64OperandType::new(op_type, op_value);
+            let (op_type, op_value, op_svcr) = op_type_value;
+            let op_type = Arm64OperandType::new(op_type, op_value, op_svcr);
             assert_eq!(expected_op_type, op_type);
         }
 
         t(
-            (ARM64_OP_INVALID, cs_arm64_op__bindgen_ty_2 { reg: 0 }),
+            (
+                ARM64_OP_INVALID,
+                cs_arm64_op__bindgen_ty_2 { reg: 0 },
+                ARM64_SVCR_INVALID,
+            ),
             Invalid,
         );
         t(
-            (ARM64_OP_REG, cs_arm64_op__bindgen_ty_2 { reg: 0 }),
+            (
+                ARM64_OP_REG,
+                cs_arm64_op__bindgen_ty_2 { reg: 0 },
+                ARM64_SVCR_INVALID,
+            ),
             Reg(RegId(0)),
         );
         t(
-            (ARM64_OP_IMM, cs_arm64_op__bindgen_ty_2 { imm: 42 }),
+            (
+                ARM64_OP_IMM,
+                cs_arm64_op__bindgen_ty_2 { imm: 42 },
+                ARM64_SVCR_INVALID,
+            ),
             Imm(42),
         );
         t(
@@ -308,6 +359,7 @@ mod test {
                 cs_arm64_op__bindgen_ty_2 {
                     reg: ARM64_SYSREG_MDRAR_EL1 as arm64_reg::Type,
                 },
+                ARM64_SVCR_INVALID,
             ),
             RegMrs(ARM64_SYSREG_MDRAR_EL1),
         );
@@ -317,15 +369,24 @@ mod test {
                 cs_arm64_op__bindgen_ty_2 {
                     pstate: ARM64_PSTATE_SPSEL,
                 },
+                ARM64_SVCR_INVALID,
             ),
             Pstate(Arm64Pstate::ARM64_PSTATE_SPSEL),
         );
         t(
-            (ARM64_OP_FP, cs_arm64_op__bindgen_ty_2 { fp: 0.0 }),
+            (
+                ARM64_OP_FP,
+                cs_arm64_op__bindgen_ty_2 { fp: 0.0 },
+                ARM64_SVCR_INVALID,
+            ),
             Fp(0.0),
         );
         t(
-            (ARM64_OP_CIMM, cs_arm64_op__bindgen_ty_2 { imm: 42 }),
+            (
+                ARM64_OP_CIMM,
+                cs_arm64_op__bindgen_ty_2 { imm: 42 },
+                ARM64_SVCR_INVALID,
+            ),
             Cimm(42),
         );
         t(
@@ -334,6 +395,7 @@ mod test {
                 cs_arm64_op__bindgen_ty_2 {
                     reg: arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1 as arm64_reg::Type,
                 },
+                ARM64_SVCR_INVALID,
             ),
             RegMsr(arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1),
         );
@@ -343,6 +405,7 @@ mod test {
                 cs_arm64_op__bindgen_ty_2 {
                     sys: arm64_sys_op::ARM64_AT_S1E0R,
                 },
+                ARM64_SVCR_INVALID,
             ),
             Sys(arm64_sys_op::ARM64_AT_S1E0R),
         );
@@ -352,8 +415,35 @@ mod test {
                 cs_arm64_op__bindgen_ty_2 {
                     prefetch: ARM64_PRFM_PLDL2KEEP,
                 },
+                ARM64_SVCR_INVALID,
             ),
             Prefetch(ARM64_PRFM_PLDL2KEEP),
         );
+        t(
+            (
+                ARM64_OP_SVCR,
+                cs_arm64_op__bindgen_ty_2 { reg: 0 },
+                ARM64_SVCR_SVCRSM,
+            ),
+            SVCR(ARM64_SVCR_SVCRSM),
+        );
+        t(
+            (
+                ARM64_OP_SME_INDEX,
+                cs_arm64_op__bindgen_ty_2 {
+                    sme_index: arm64_op_sme_index {
+                        reg: 1,
+                        base: 2,
+                        disp: 3,
+                    },
+                },
+                ARM64_SVCR_INVALID,
+            ),
+            SMEIndex(Arm64OpSmeIndex(arm64_op_sme_index {
+                reg: 1,
+                base: 2,
+                disp: 3,
+            })),
+        );
     }
 }

capstone-rs/src/arch/mod.rs

@@ -326,7 +326,22 @@ macro_rules! arch_info_base {
                     )
                 ( extra_modes: )
                 ( syntax: )
-                ( both_endian: false )
+                ( both_endian: true )
+            ]
+            [
+                ( tricore, TriCore )
+                ( mode:
+                    TriCore110,
+                    TriCore120,
+                    TriCore130,
+                    TriCore131,
+                    TriCore160,
+                    TriCore161,
+                    TriCore162,
+                    )
+                ( extra_modes: )
+                ( syntax: )
+                ( both_endian: true )
             ]
             [
                 ( x86, X86 )
@@ -530,6 +545,13 @@ macro_rules! detail_arch_base {
                 /// Returns the Tms320c64x details, if any
                 => arch_name = tms320c64x,
             ]
+            [
+                detail = TriCoreDetail,
+                insn_detail = TriCoreInsnDetail<'a>,
+                op = TriCoreOperand,
+                /// Returns the TriCore details, if any
+                => arch_name = tricore,
+            ]
             [
                 detail = X86Detail,
                 insn_detail = X86InsnDetail<'a>,

capstone-rs/src/arch/tricore.rs

@@ -0,0 +1,91 @@
+//! Contains tricore-specific types
+
+use core::convert::From;
+use core::{cmp, fmt, slice};
+
+pub use capstone_sys::tricore_insn as TriCoreInsn;
+pub use capstone_sys::tricore_insn_group as TriCoreInsnGroup;
+pub use capstone_sys::tricore_reg as TriCoreReg;
+use capstone_sys::{cs_tricore, cs_tricore_op, tricore_op_mem, tricore_op_type};
+
+pub use crate::arch::arch_builder::tricore::*;
+use crate::arch::DetailsArchInsn;
+use crate::instruction::{RegId, RegIdInt};
+
+/// Contains tricore-specific details for an instruction
+pub struct TriCoreInsnDetail<'a>(pub(crate) &'a cs_tricore);
+
+impl_PartialEq_repr_fields!(TriCoreInsnDetail<'a> [ 'a ];
+    operands
+);
+
+/// tricore operand
+#[derive(Clone, Debug, Eq, PartialEq)]
+pub enum TriCoreOperand {
+    /// Register
+    Reg(RegId),
+
+    /// Immediate
+    Imm(i32),
+
+    /// Memory
+    Mem(TriCoreOpMem),
+
+    /// Invalid
+    Invalid,
+}
+
+impl Default for TriCoreOperand {
+    fn default() -> Self {
+        TriCoreOperand::Invalid
+    }
+}
+
+/// tricore memory operand
+#[derive(Debug, Copy, Clone)]
+pub struct TriCoreOpMem(pub(crate) tricore_op_mem);
+
+impl TriCoreOpMem {
+    /// Base register
+    pub fn base(&self) -> RegId {
+        RegId(RegIdInt::from(self.0.base))
+    }
+
+    /// Disp value
+    pub fn disp(&self) -> i32 {
+        self.0.disp
+    }
+}
+
+impl_PartialEq_repr_fields!(TriCoreOpMem;
+    base, disp
+);
+
+impl cmp::Eq for TriCoreOpMem {}
+
+impl From<&cs_tricore_op> for TriCoreOperand {
+    fn from(insn: &cs_tricore_op) -> TriCoreOperand {
+        match insn.type_ {
+            tricore_op_type::TRICORE_OP_REG => {
+                TriCoreOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
+            }
+            tricore_op_type::TRICORE_OP_IMM => {
+                TriCoreOperand::Imm(unsafe { insn.__bindgen_anon_1.imm })
+            }
+            tricore_op_type::TRICORE_OP_MEM => {
+                TriCoreOperand::Mem(TriCoreOpMem(unsafe { insn.__bindgen_anon_1.mem }))
+            }
+            tricore_op_type::TRICORE_OP_INVALID => TriCoreOperand::Invalid,
+        }
+    }
+}
+
+def_arch_details_struct!(
+    InsnDetail = TriCoreInsnDetail;
+    Operand = TriCoreOperand;
+    OperandIterator = TriCoreOperandIterator;
+    OperandIteratorLife = TriCoreOperandIterator<'a>;
+    [ pub struct TriCoreOperandIterator<'a>(slice::Iter<'a, cs_tricore_op>); ]
+    cs_arch_op = cs_tricore_op;
+    cs_arch = cs_tricore;
+);

capstone-rs/src/constants.rs

@@ -216,6 +216,8 @@ define_cs_enum_wrapper!(
     => M68K = CS_ARCH_M68K;
     /// Texas Instruments TMS320C64x
     => TMS320C64X = CS_ARCH_TMS320C64X;
+    /// TriCore
+    => TriCore = CS_ARCH_TRICORE;
     /// Motorola 68000
     => M680X = CS_ARCH_M680X;
     /// EVM
@@ -293,6 +295,20 @@ define_cs_enum_wrapper!(
     => Cbpf = { cs_mode::CS_MODE_BPF_CLASSIC };
     /// Extended BPF mode
     => Ebpf = { cs_mode::CS_MODE_BPF_EXTENDED };
+    /// TriCore 1.1
+    => TriCore110 = { cs_mode::CS_MODE_TRICORE_110 };
+    /// TriCore 1.2
+    => TriCore120 = { cs_mode::CS_MODE_TRICORE_120 };
+    /// TriCore 1.3
+    => TriCore130 = { cs_mode::CS_MODE_TRICORE_130 };
+    /// TriCore 1.3.1
+    => TriCore131 = { cs_mode::CS_MODE_TRICORE_131 };
+    /// TriCore 1.6
+    => TriCore160 = { cs_mode::CS_MODE_TRICORE_160 };
+    /// TriCore 1.6.1
+    => TriCore161 = { cs_mode::CS_MODE_TRICORE_161 };
+    /// TriCore 1.6.2
+    => TriCore162 = { cs_mode::CS_MODE_TRICORE_162 };
     /// Default mode for little-endian
     => Default = { cs_mode::CS_MODE_LITTLE_ENDIAN };
 );