improve timer performance

Author: ccattuto

cpu.py

@@ -18,7 +18,6 @@
 from machine import MachineError, ExecutionTerminated, SetupError
 import random
 
-# Helper functions
 
 def signed32(val):
     return val if val < 0x80000000 else val - 0x100000000
@@ -237,6 +236,7 @@ def exec_SYSTEM(cpu, ram, inst, rd, funct3, rs1, rs2, funct7):
                     cpu.mtime = (cpu.csrs[0x7C1] << 32) | cpu.csrs[0x7C0]
                     cpu.mtime_lo_updated = False
                     cpu.mtime_hi_updated = False
+                    cpu.mtip = (cpu.mtime >= cpu.mtimecmp)
 
             # Atomic update of mtimecmp
             if csr in (0x7C2, 0x7C3):
@@ -246,7 +246,9 @@ def exec_SYSTEM(cpu, ram, inst, rd, funct3, rs1, rs2, funct7):
                     cpu.mtimecmp = (cpu.csrs[0x7C3] << 32) | cpu.csrs[0x7C2]
                     cpu.mtimecmp_lo_updated = False
                     cpu.mtimecmp_hi_updated = False
-        
+                    cpu.mtime_countdown = cpu.mtimecmp - cpu.mtime
+                    cpu.mtip = (cpu.mtime >= cpu.mtimecmp)
+
         elif funct3 in (0b010, 0b110):  # CSRRS / CSRRSI
             if rs1_val != 0:
                 cpu.csrs[csr] = old | rs1_val
@@ -335,6 +337,7 @@ def __init__(self, ram, init_regs=None, logger=None, args=None):
         self.mtime_hi_updated = False
         self.mtimecmp_lo_updated = False
         self.mtimecmp_hi_updated = False
+        self.mtip = False
 
         # name - ID register maps
         self.REG_NUM_NAME = {}
@@ -418,20 +421,30 @@ def bypassed_trap_return(self, cause, mtval=0):
         self.csrs[0x300] |= (1 << 7)        # MPIE = 1
         # (MIE, bit 3, stays unchanged)
 
+    # Machine timer interrupt logic
     def timer_update(self):
         csrs = self.csrs
-        self.mtime = (self.mtime + 1) & 0xFFFFFFFF_FFFFFFFF
+        mtime = self.mtime
 
-        # trigger Machine Timer Interrupt
-        if self.mtime >= self.mtimecmp:
-            csrs[0x344] |= (1 << 7)     # set MTIP (timer interrupt)
-        else:
-            csrs[0x344] &= ~(1 << 7)    # clear MTIP
+        self.mtime = (mtime + 1) # & 0xFFFFFFFF_FFFFFFFF  # the counter should wrap, but it's unlikely to ever happen ;)
+        mtip_asserted = (mtime >= self.mtimecmp)
 
-        if (csrs[0x300] & (1<<3)) and (csrs[0x304] & (1<<7)) and (csrs[0x344] & (1<<7)):
-            self.trap(cause=0x80000007, sync=False)  # fire interrupt as an asynchronous trap
+        # Set interrupt pending flag
+        if mtip_asserted != self.mtip:
+            if mtip_asserted:
+                csrs[0x344] |= (1 << 7)     # set MTIP
+            else:
+                csrs[0x344] &= ~(1 << 7)    # clear MTIP
+            self.mtip = mtip_asserted
+
+        if not mtip_asserted:
+            return
+        
+        # Trigger Machine Timer Interrupt
+        if (csrs[0x300] & (1<<3)) and (csrs[0x304] & (1<<7)):
+            self.trap(cause=0x80000007, sync=False)  # fire timer interrupt as an asynchronous trap
 
-    # CPU register initialization
+    # CPU registers initialization
     def init_registers(self, mode='0x00000000'):
         self.registers[0] = 0
         if mode == 'random':

machine.py

@@ -207,17 +207,17 @@ def make_regformatter_lambda(self, regstring='pc,sp,ra,a0'):
 
         getters = []
         for name in names:
-            if name in cpu.REG_NAME_NUM:
+            if name in cpu.REG_NAME_NUM:  # registers
                 idx = cpu.REG_NAME_NUM[name]
                 getters.append( (name, lambda cpu, idx=idx: cpu.registers[idx]) )
-            elif name in ['mtime_lo', 'mtimecmp_lo']:
+            elif name in ['mtime_lo', 'mtimecmp_lo']:  # mtime/mtimecmp
                 getters.append( (name, lambda cpu, name=name: getattr(cpu, name[:-3]) & 0xFFFFFFFF) )
-            elif name in ['mtime_hi', 'mtimecmp_hi']:
+            elif name in ['mtime_hi', 'mtimecmp_hi']:  # mtime/mtimecmp
                 getters.append( (name, lambda cpu, name=name: getattr(cpu, name[:-3]) >> 32) )
-            elif name in cpu.CSR_NAME_ADDR:
+            elif name in cpu.CSR_NAME_ADDR:  # CSRs
                 addr = cpu.CSR_NAME_ADDR[name]
                 getters.append( (name, lambda cpu, addr=addr: cpu.csrs[addr]) )
-            elif name in ['pc']:
+            elif name in ['pc']:  #PC
                 getters.append( (name, lambda cpu, name=name: getattr(cpu, name)) )
             else:
                 raise SetupError(f"Unknown register/CSR while setting up register logging: '{name}'")