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alaindargelasalaindargelas
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fix
1 parent 40bc8de commit 4c24df2

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Lines changed: 59 additions & 82 deletions

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‎src/DesignCompile/CompileExpression.cpp‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4514,14 +4514,20 @@ UHDM::any *CompileHelper::compileBits(
45144514
}
45154515
}
45164516

4517-
if ((reduce == Reduce::Yes) && tps && (!invalidValue)) {
4517+
// For `$size`, defer to the sys_func_call form so the elaboration
4518+
// step's `reduceExpr` evaluates the dim-index argument correctly.
4519+
// `Bits()`/`eval.size()` (called above) only inspects the FIRST
4520+
// argument's typespec — it ignores the dim-index entirely and uses
4521+
// the wrong range (`ranges->back()`) for multi-dim types. For
4522+
// `$bits` the folded value is still right (sum of all bits).
4523+
if ((reduce == Reduce::Yes) && tps && (!invalidValue) && !sizeMode) {
45184524
UHDM::constant *c = s.MakeConstant();
45194525
c->VpiValue("UINT:" + std::to_string(bits));
45204526
c->VpiDecompile(std::to_string(bits));
45214527
c->VpiConstType(vpiUIntConst);
45224528
c->VpiSize(64);
45234529
result = c;
4524-
} else if ((reduce == Reduce::Yes) && exp && (!invalidValue)) {
4530+
} else if ((reduce == Reduce::Yes) && exp && (!invalidValue) && !sizeMode) {
45254531
UHDM::constant *c = s.MakeConstant();
45264532
c->VpiValue("UINT:" + std::to_string(bits));
45274533
c->VpiDecompile(std::to_string(bits));

‎tests/NonSynthError/NonSynthError.log‎

Lines changed: 20 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -75,29 +75,27 @@ AST_DEBUG_END
7575
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
7676
begin 1
7777
class_defn 1
78-
constant 3
7978
design 1
8079
initial 1
81-
int_typespec 4
80+
int_typespec 3
81+
int_var 3
8282
module_inst 5
8383
param_assign 2
8484
parameter 2
85-
ref_typespec 5
86-
sys_func_call 1
85+
sys_func_call 4
8786
=== UHDM Object Stats End ===
8887
[INF:UH0707] Elaborating UHDM...
8988
=== UHDM Object Stats Begin (Elaborated Model) ===
9089
begin 2
9190
class_defn 2
92-
constant 3
9391
design 1
9492
initial 2
95-
int_typespec 4
93+
int_typespec 3
94+
int_var 3
9695
module_inst 5
9796
param_assign 2
9897
parameter 2
99-
ref_typespec 5
100-
sys_func_call 2
98+
sys_func_call 5
10199
=== UHDM Object Stats End ===
102100
[WRN:UH0720] ${SURELOG_DIR}/tests/NonSynthError/dut.sv:10:1: Non-synthesizable construct "A".
103101
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/NonSynthError/slpp_all/surelog.uhdm ...
@@ -117,35 +115,22 @@ design: (work@dut)
117115
\_parameter: (work@dut.S), line:4:11, endln:4:12
118116
|vpiParent:
119117
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10
120-
|UINT:32
121-
|vpiTypespec:
122-
\_ref_typespec: (work@dut.S)
123-
|vpiParent:
124-
\_parameter: (work@dut.S), line:4:11, endln:4:12
125-
|vpiFullName:work@dut.S
126-
|vpiActual:
127-
\_int_typespec: , line:4:1, endln:4:25
128118
|vpiName:S
129119
|vpiFullName:work@dut.S
130120
|vpiParamAssign:
131121
\_param_assign: , line:4:11, endln:4:25
132122
|vpiParent:
133123
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10
134124
|vpiRhs:
135-
\_constant: , line:4:15, endln:4:20
125+
\_sys_func_call: ($size), line:4:15, endln:4:20
136126
|vpiParent:
137127
\_param_assign: , line:4:11, endln:4:25
138-
|vpiDecompile:32
139-
|vpiSize:64
140-
|UINT:32
141-
|vpiTypespec:
142-
\_ref_typespec: (work@dut)
128+
|vpiArgument:
129+
\_int_var: (work@dut), line:4:21, endln:4:24
143130
|vpiParent:
144-
\_constant: , line:4:15, endln:4:20
131+
\_sys_func_call: ($size), line:4:15, endln:4:20
145132
|vpiFullName:work@dut
146-
|vpiActual:
147-
\_int_typespec: , line:4:1, endln:4:25
148-
|vpiConstType:9
133+
|vpiName:$size
149134
|vpiLhs:
150135
\_parameter: (work@dut.S), line:4:11, endln:4:12
151136
|vpiDefName:work@dut
@@ -173,35 +158,22 @@ design: (work@dut)
173158
\_parameter: (work@dut.S), line:4:11, endln:4:12
174159
|vpiParent:
175160
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10
176-
|UINT:32
177-
|vpiTypespec:
178-
\_ref_typespec: (work@dut.S)
179-
|vpiParent:
180-
\_parameter: (work@dut.S), line:4:11, endln:4:12
181-
|vpiFullName:work@dut.S
182-
|vpiActual:
183-
\_int_typespec: , line:4:1, endln:4:25
184161
|vpiName:S
185162
|vpiFullName:work@dut.S
186163
|vpiParamAssign:
187164
\_param_assign: , line:4:11, endln:4:25
188165
|vpiParent:
189166
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonSynthError/dut.sv, line:2:1, endln:13:10
190167
|vpiRhs:
191-
\_constant: , line:4:15, endln:4:25
168+
\_sys_func_call: ($size), line:4:15, endln:4:20
192169
|vpiParent:
193170
\_param_assign: , line:4:11, endln:4:25
194-
|vpiDecompile:32
195-
|vpiSize:32
196-
|UINT:32
197-
|vpiTypespec:
198-
\_ref_typespec: (work@dut)
171+
|vpiArgument:
172+
\_int_var: (work@dut), line:4:21, endln:4:24
199173
|vpiParent:
200-
\_constant: , line:4:15, endln:4:25
174+
\_sys_func_call: ($size), line:4:15, endln:4:20
201175
|vpiFullName:work@dut
202-
|vpiActual:
203-
\_int_typespec: , line:4:1, endln:4:25
204-
|vpiConstType:9
176+
|vpiName:$size
205177
|vpiLhs:
206178
\_parameter: (work@dut.S), line:4:11, endln:4:12
207179
|vpiDefName:work@dut
@@ -222,11 +194,6 @@ design: (work@dut)
222194
|vpiParent:
223195
\_initial: , line:6:1, endln:8:4
224196
|vpiFullName:work@dut
225-
\_weaklyReferenced:
226-
\_int_typespec: , line:4:1, endln:4:25
227-
\_int_typespec: , line:4:1, endln:4:25
228-
|vpiParent:
229-
\_ref_typespec: (work@dut.S)
230197
===================
231198
[ FATAL] : 0
232199
[ SYNTAX] : 0
@@ -238,3 +205,7 @@ design: (work@dut)
238205
[LINT]: ${SURELOG_DIR}/tests/NonSynthError/dut.sv:10:1: Non synthesizable construct, A
239206
[LINT]: ${SURELOG_DIR}/tests/NonSynthError/dut.sv:10:1: Non synthesizable construct, A
240207
============================== End Linting Results ==============================
208+
209+
============================== Begin RoundTrip Results ==============================
210+
[roundtrip]: ${SURELOG_DIR}/tests/NonSynthError/dut.sv | ${SURELOG_DIR}/build/regression/NonSynthError/roundtrip/dut_000.sv | 2 | 13 |
211+
============================== End RoundTrip Results ==============================

‎tests/SystemCallSize/SystemCallSize.log‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -255,9 +255,9 @@ module_inst 5
255255
operation 7
256256
parameter 2
257257
range 17
258-
ref_obj 8
258+
ref_obj 12
259259
ref_typespec 19
260-
sys_func_call 2
260+
sys_func_call 6
261261
=== UHDM Object Stats End ===
262262
[INF:UH0707] Elaborating UHDM...
263263
=== UHDM Object Stats Begin (Elaborated Model) ===
@@ -279,9 +279,9 @@ module_inst 5
279279
operation 7
280280
parameter 2
281281
range 17
282-
ref_obj 10
282+
ref_obj 14
283283
ref_typespec 21
284-
sys_func_call 2
284+
sys_func_call 6
285285
=== UHDM Object Stats End ===
286286
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/SystemCallSize/slpp_all/surelog.uhdm ...
287287
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/SystemCallSize/slpp_all/checker/surelog.chk.html ...

‎third_party/UHDM‎

‎third_party/tests/CoresSweRVMP/CoresSweRVMP.log‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -64,19 +64,19 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
6464
-- Configuring done
6565
-- Generating done
6666
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
67-
[ 12%] Generating 10_lsu_bus_intf.sv
68-
[ 12%] Generating 11_ifu_bp_ctl.sv
69-
[ 18%] Generating 13_ifu_mem_ctl.sv
70-
[ 25%] Generating 12_beh_lib.sv
71-
[ 31%] Generating 14_mem_lib.sv
72-
[ 37%] Generating 15_exu.sv
73-
[ 43%] Generating 16_dec_decode_ctl.sv
67+
[ 6%] Generating 10_lsu_bus_intf.sv
68+
[ 12%] Generating 15_exu.sv
69+
[ 18%] Generating 14_mem_lib.sv
70+
[ 25%] Generating 13_ifu_mem_ctl.sv
71+
[ 31%] Generating 11_ifu_bp_ctl.sv
72+
[ 37%] Generating 16_dec_decode_ctl.sv
73+
[ 43%] Generating 12_beh_lib.sv
7474
[ 50%] Generating 1_lsu_stbuf.sv
7575
[ 56%] Generating 2_ahb_to_axi4.sv
7676
[ 62%] Generating 3_rvjtag_tap.sv
7777
[ 68%] Generating 4_dec_tlu_ctl.sv
78-
[ 75%] Generating 6_dbg.sv
79-
[ 81%] Generating 5_lsu_bus_buffer.sv
78+
[ 75%] Generating 5_lsu_bus_buffer.sv
79+
[ 81%] Generating 6_dbg.sv
8080
[ 87%] Generating 7_axi4_to_ahb.sv
8181
[ 93%] Generating 8_ifu_aln_ctl.sv
8282
[100%] Generating 9_tb_top.sv

‎third_party/tests/IbexGoogle/IbexGoogle.log‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -483,7 +483,7 @@ chandle_var 2
483483
class_defn 706
484484
class_typespec 17862
485485
class_var 9573
486-
constant 95429
486+
constant 95428
487487
constraint 40
488488
continue_stmt 133
489489
delay_control 129
@@ -532,7 +532,7 @@ part_select 189
532532
range 16740
533533
real_typespec 41
534534
real_var 8
535-
ref_obj 110782
535+
ref_obj 110783
536536
ref_typespec 59063
537537
ref_var 4642
538538
repeat 73
@@ -541,7 +541,7 @@ string_typespec 7569
541541
string_var 3523
542542
struct_typespec 112
543543
struct_var 112
544-
sys_func_call 3559
544+
sys_func_call 3560
545545
tagged_pattern 23
546546
task 1002
547547
task_call 38

‎third_party/tests/NyuziProcessor/NyuziProcessor.log‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -893,7 +893,7 @@ case_stmt 141
893893
class_defn 8
894894
class_typespec 4
895895
class_var 3
896-
constant 141202
896+
constant 141204
897897
cont_assign 2227
898898
design 1
899899
enum_const 13261
@@ -917,7 +917,7 @@ import_typespec 49
917917
include_file_info 98
918918
indexed_part_select 689
919919
initial 16
920-
int_typespec 85383
920+
int_typespec 85377
921921
int_var 92
922922
integer_typespec 121
923923
integer_var 1
@@ -926,7 +926,7 @@ interface_inst 48
926926
interface_typespec 104
927927
io_decl 831
928928
logic_net 3747
929-
logic_typespec 20996
929+
logic_typespec 20998
930930
logic_var 2684
931931
modport 77
932932
module_array 3
@@ -941,16 +941,16 @@ param_assign 52436
941941
parameter 76277
942942
part_select 435
943943
port 3875
944-
range 18477
944+
range 18479
945945
ref_module 187
946-
ref_obj 33530
947-
ref_typespec 138196
946+
ref_obj 33539
947+
ref_typespec 138195
948948
string_typespec 84
949949
string_var 1
950950
struct_net 81
951951
struct_typespec 1093
952952
struct_var 77
953-
sys_func_call 2605
953+
sys_func_call 2608
954954
task 13
955955
task_call 11
956956
typespec_member 7460
@@ -973,7 +973,7 @@ case_stmt 434
973973
class_defn 8
974974
class_typespec 4
975975
class_var 3
976-
constant 143736
976+
constant 143738
977977
cont_assign 5561
978978
design 1
979979
enum_const 13266
@@ -997,7 +997,7 @@ import_typespec 49
997997
include_file_info 98
998998
indexed_part_select 1611
999999
initial 189
1000-
int_typespec 85383
1000+
int_typespec 85377
10011001
int_var 253
10021002
integer_typespec 121
10031003
integer_var 1
@@ -1006,7 +1006,7 @@ interface_inst 48
10061006
interface_typespec 104
10071007
io_decl 845
10081008
logic_net 3747
1009-
logic_typespec 20996
1009+
logic_typespec 20998
10101010
logic_var 6035
10111011
modport 77
10121012
module_array 3
@@ -1021,16 +1021,16 @@ param_assign 83958
10211021
parameter 76277
10221022
part_select 1178
10231023
port 7457
1024-
range 18627
1024+
range 18629
10251025
ref_module 187
1026-
ref_obj 90421
1027-
ref_typespec 203156
1026+
ref_obj 90430
1027+
ref_typespec 203155
10281028
string_typespec 84
10291029
string_var 1
10301030
struct_net 81
10311031
struct_typespec 1093
10321032
struct_var 135
1033-
sys_func_call 3567
1033+
sys_func_call 3570
10341034
task 26
10351035
task_call 22
10361036
typespec_member 7460

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