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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.5k 640

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.6k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.7k 263

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.2k 362

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 912 234

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 748 179

Repositories

Showing 10 of 112 repositories
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 128 Apache-2.0 73 198 79 Updated Nov 28, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,482 Apache-2.0 640 345 (1 issue needs help) 148 Updated Nov 28, 2025
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 37 Apache-2.0 13 16 2 Updated Nov 28, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 41 LGPL-3.0 729 0 0 Updated Nov 28, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 350 ISC 84 46 (4 issues need help) 29 Updated Nov 27, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 21 Apache-2.0 26 87 (1 issue needs help) 13 Updated Nov 27, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 33 Apache-2.0 31 70 9 Updated Nov 27, 2025
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra’s past year of commit activity
    351 Apache-2.0 54 54 9 Updated Nov 26, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 302 Apache-2.0 41 18 28 Updated Nov 26, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 116 Apache-2.0 67 86 17 Updated Nov 25, 2025