gen block binding

Author: alaindargelas

tests/GenScopeShadow/GenScopeShadow.log

@@ -0,0 +1 @@
+-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin

tests/GenScopeShadow/GenScopeShadow.sl

@@ -0,0 +1,16 @@
+`default_nettype none
+
+module gate(out);
+    wire [3:0] x;
+    for (genvar x = 0; x < 2; x++) begin : blk
+        localparam w = x;
+        if (x == 0) begin : sub
+            wire [w:0] x;
+        end
+    end
+    //assign x = 2;
+    assign blk[0].sub.x = '1;
+    //output wire [9:0] out;
+    //assign out = {1'bx, x, blk[0].sub.x};
+endmodule
+

tests/GenScopeShadow/dut.sv

@@ -0,0 +1 @@
+-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin

tests/GenVarRef/GenVarRef.log

@@ -0,0 +1,9 @@
+`default_nettype none
+
+module gate(a);
+	for (genvar i = 0; i < 2; i++)
+		wire [i:0] x = '1;
+
+	output wire [32:0] a;
+	assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0};
+endmodule

tests/GenVarRef/GenVarRef.sl

@@ -797,6 +797,8 @@ design: (work@top)
         |vpiParent:
         \_hier_path: (genblk1.foo.x1), line:67:16, endln:67:30
         |vpiName:x1
+        |vpiActual:
+        \_logic_net: (work@top.genblk1.foo.x1), line:38:38, endln:38:40
       |vpiName:genblk1.foo.x1
   |vpiContAssign:
   \_cont_assign: , line:68:16, endln:68:29
@@ -902,6 +904,8 @@ design: (work@top)
         |vpiParent:
         \_hier_path: (bar2.baz.x3), line:71:16, endln:71:27
         |vpiName:x3
+        |vpiActual:
+        \_logic_net: (work@top.bar2.baz.x3), line:58:38, endln:58:40
       |vpiName:bar2.baz.x3
   |vpiContAssign:
   \_cont_assign: , line:72:16, endln:72:31
@@ -932,6 +936,8 @@ design: (work@top)
         |vpiParent:
         \_hier_path: (bar2.baz.z3), line:72:16, endln:72:27
         |vpiName:z3
+        |vpiActual:
+        \_logic_net: (work@top.bar2.baz.z3), line:59:37, endln:59:39
       |vpiName:bar2.baz.z3
 \_weaklyReferenced:
 \_logic_typespec: , line:35:25, endln:35:29

tests/GenVarRef/dut.sv

@@ -67,10 +67,10 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 [  6%] Generating 10_lsu_bus_intf.sv
 [ 12%] Generating 11_ifu_bp_ctl.sv
 [ 18%] Generating 12_beh_lib.sv
-[ 25%] Generating 13_ifu_mem_ctl.sv
-[ 31%] Generating 14_mem_lib.sv
+[ 25%] Generating 14_mem_lib.sv
+[ 31%] Generating 13_ifu_mem_ctl.sv
 [ 37%] Generating 15_exu.sv
-[ 43%] Generating 16_dec_decode_ctl.sv
+[ 50%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv
 [ 62%] Generating 3_rvjtag_tap.sv