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alaindargelasalaindargelas
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Merge pull request #4075 from alainmarcel/wire_type
wire type
2 parents 032128c + 98ffd45 commit f229a8b

7 files changed

Lines changed: 2927 additions & 22 deletions

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‎include/Surelog/Design/Signal.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,10 @@ class Signal final {
6969
void setModPort(ModPort* modport) { m_modPort = modport; }
7070
void setDirection(VObjectType direction) { m_direction = direction; }
7171
void setType(VObjectType type) { m_type = type; }
72+
// For typed net declarations (e.g. "wand integer"), stores the original net
73+
// keyword (paNetType_Wand/Wor/Wire) separate from the data type in m_type.
74+
VObjectType getSubNetType() const { return m_subNetType; }
75+
void setSubNetType(VObjectType t) { m_subNetType = t; }
7276
void setDataType(const DataType* dtype) { m_dataType = dtype; }
7377
void setPackedDimension(NodeId id) { m_packedDimension = id; }
7478
void setUnpackedDimension(NodeId id) { m_unpackedDimension = id; }
@@ -116,6 +120,10 @@ class Signal final {
116120
const FileContent* m_fileContent = nullptr;
117121
NodeId m_nodeId;
118122
VObjectType m_type = VObjectType::slNoType;
123+
// Preserved original net keyword for typed net declarations (e.g., "wand integer").
124+
// When set, m_type holds the data type (e.g., paIntegerAtomType_Integer) and
125+
// m_subNetType holds the net keyword (e.g., paNetType_Wand).
126+
VObjectType m_subNetType = VObjectType::slNoType;
119127
VObjectType m_direction = VObjectType::slNoType;
120128
ModuleDefinition* m_interfaceDef = nullptr;
121129
ModPort* m_modPort = nullptr;

‎src/DesignCompile/CompileHelper.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2187,6 +2187,9 @@ bool CompileHelper::compileNetDeclaration(DesignComponent* component,
21872187
sig->setTypespecId(NetType);
21882188
sig->attributes(attributes);
21892189
if (isSigned) sig->setSigned();
2190+
// Preserve the original net keyword (e.g. wand/wor) for typed net decls
2191+
// like "wand typename". ElaborationStep may later overwrite m_type.
2192+
if (subnettype != VObjectType::slNoType) sig->setSubNetType(subnettype);
21902193
component->getSignals().push_back(sig);
21912194
} else {
21922195
Signal* sig =
@@ -2197,6 +2200,9 @@ bool CompileHelper::compileNetDeclaration(DesignComponent* component,
21972200
sig->setStatic();
21982201
sig->attributes(attributes);
21992202
if (isSigned) sig->setSigned();
2203+
// Preserve the original net keyword (e.g. wand/wor) for typed net decls
2204+
// like "wand integer" where nettype was overwritten by the data type.
2205+
if (subnettype != VObjectType::slNoType) sig->setSubNetType(subnettype);
22002206
component->getSignals().push_back(sig);
22012207
}
22022208

‎src/DesignCompile/NetlistElaboration.cpp‎

Lines changed: 21 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1838,6 +1838,10 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
18381838
// Nets pass
18391839
const DataType* dtype = sig->getDataType();
18401840
VObjectType subnettype = sig->getType();
1841+
// For typed net declarations (e.g. "wand integer"), the original net keyword
1842+
// (paNetType_Wand/Wor/Wire) is preserved in getSubNetType(). The m_type
1843+
// (subnettype) holds the data type which may have overridden the net keyword.
1844+
VObjectType netKeyword = sig->getSubNetType();
18411845
UHDM::typespec* tps = nullptr;
18421846
// Determine if the "signal" is a net or a var
18431847
bool isNet = true;
@@ -1868,6 +1872,11 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
18681872
isNet = true;
18691873
}
18701874
}
1875+
// Typed net declarations like "wand integer" or "wand typename" store the
1876+
// original net keyword in getSubNetType(). Override isNet for these cases.
1877+
if (netKeyword != VObjectType::slNoType) {
1878+
isNet = true;
1879+
}
18711880

18721881
NodeId typeSpecId = sig->getTypeSpecId();
18731882
if (typeSpecId) {
@@ -1990,7 +1999,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
19901999
for (auto a : *sig->attributes()) a->VpiParent(logicn);
19912000
}
19922001
logicn->VpiSigned(sig->isSigned());
1993-
logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2002+
logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
19942003
// Move range to typespec for simple types
19952004
// logicn->Ranges(packedDimensions);
19962005
ref_typespec* rt = s.MakeRef_typespec();
@@ -2106,9 +2115,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
21062115
stv->VpiParent(pnets);
21072116
for (auto r : *packedDimensions) r->VpiParent(pnets);
21082117
obj = pnets;
2109-
pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2118+
pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
21102119
} else {
2111-
stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2120+
stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
21122121
}
21132122
} else if (const Struct* st = datatype_cast<const Struct*>(dtype)) {
21142123
struct_net* stv = s.MakeStruct_net();
@@ -2130,9 +2139,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
21302139
stv->VpiParent(pnets);
21312140
for (auto r : *packedDimensions) r->VpiParent(pnets);
21322141
obj = pnets;
2133-
pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2142+
pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
21342143
} else {
2135-
stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2144+
stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
21362145
}
21372146
} else if (dtype->getCategory() == DataType::Category::PARAMETER ||
21382147
dtype->getCategory() == DataType::Category::SIMPLE_TYPEDEF) {
@@ -2154,7 +2163,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
21542163
for (auto a : *sig->attributes()) a->VpiParent(logicn);
21552164
}
21562165
logicn->VpiSigned(sig->isSigned());
2157-
logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2166+
logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
21582167
// Move range to typespec for simple types
21592168
// logicn->Ranges(packedDimensions);
21602169
ref_typespec* rt = s.MakeRef_typespec();
@@ -2185,9 +2194,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
21852194
stv->VpiParent(pnets);
21862195
for (auto r : *packedDimensions) r->VpiParent(pnets);
21872196
obj = pnets;
2188-
pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2197+
pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
21892198
} else {
2190-
stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2199+
stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
21912200
}
21922201
} else if (spec->UhdmType() == uhdmenum_typespec) {
21932202
enum_net* stv = s.MakeEnum_net();
@@ -2210,9 +2219,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
22102219
stv->VpiParent(pnets);
22112220
for (auto r : *packedDimensions) r->VpiParent(pnets);
22122221
obj = pnets;
2213-
pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2222+
pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
22142223
} else {
2215-
stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2224+
stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
22162225
}
22172226
} else if (spec->UhdmType() == uhdmbit_typespec) {
22182227
bit_var* logicn = s.MakeBit_var();
@@ -2265,7 +2274,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
22652274
for (auto a : *sig->attributes()) a->VpiParent(logicn);
22662275
}
22672276
logicn->VpiSigned(sig->isSigned());
2268-
logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2277+
logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
22692278
ref_typespec* rt = s.MakeRef_typespec();
22702279
rt->VpiParent(logicn);
22712280
rt->Actual_typespec(tps);
@@ -2370,7 +2379,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
23702379
} else {
23712380
logic_net* logicn = s.MakeLogic_net();
23722381
logicn->VpiSigned(sig->isSigned());
2373-
logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
2382+
logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
23742383
if (sig->attributes()) {
23752384
logicn->Attributes(sig->attributes());
23762385
for (auto a : *sig->attributes()) a->VpiParent(logicn);

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