test multirange access

wsipak · wsipak · commit cfe1e456b4c3 · 2023-06-16T15:02:11.000+02:00
diff --git a/tests/MultirangeAccess/Makefile.in b/tests/MultirangeAccess/Makefile.in
@@ -0,0 +1,2 @@
+TOP_FILE := $(TEST_DIR)/top.sv
+TOP_MODULE := top
diff --git a/tests/MultirangeAccess/top.sv b/tests/MultirangeAccess/top.sv
@@ -0,0 +1,8 @@
+typedef logic [3:0][7:0] my_struct_packed_t;
+
+module top (
+    input  my_struct_packed_t x,
+    output my_struct_packed_t y
+);
+   assign y[2][1] = x[1][0];
+endmodule : top
diff --git a/tests/MultirangeAccess/yosys_script.tcl b/tests/MultirangeAccess/yosys_script.tcl
@@ -0,0 +1,5 @@
+source ../yosys_common.tcl
+
+prep -top \\top
+write_verilog
+write_verilog yosys.sv
