cleaning up sk encode states created overlapping cases as it was unclear the two parameter definitions overlapped.

norm check failures in the last sample were getting missed, caught in regression
abr ctrl was leaving data in the api reg, needs to clear it when reading

Author: Nitsirks

src/abr_top/rtl/abr_ctrl.sv

@@ -1070,11 +1070,11 @@ always_comb kv_mlkem_msg_write_data = '0;
     end else if (zeroize) begin
       api_reg_rdata <= '0;
     end else begin
-      if      (api_keymem_rd_vld & api_sk_reg_rd_dec)      api_reg_rdata <= abr_scratch_reg.raw[api_sk_reg_raddr];
-      else if (mlkem_api_dk_rd_vld & mlkem_api_dk_reg_dec) api_reg_rdata <= abr_scratch_reg.raw[mlkem_api_dk_reg_addr];
-      else if (mlkem_api_ek_rd_vld & mlkem_api_ek_reg_dec) api_reg_rdata <= abr_scratch_reg.raw[mlkem_api_ek_reg_addr];    
-      else if (mldsa_valid_reg & api_pubkey_rho_dec)       api_reg_rdata <= abr_scratch_reg.raw[api_pk_reg_raddr];
-      else if (mldsa_valid_reg & api_sig_reg_re)           api_reg_rdata <= signature_reg_rdata;
+      if      (api_sk_reg_rd_dec)    api_reg_rdata <= {ABR_REG_WIDTH{api_keymem_rd_vld}} & abr_scratch_reg.raw[api_sk_reg_raddr];
+      else if (mlkem_api_dk_reg_dec) api_reg_rdata <= {ABR_REG_WIDTH{mlkem_api_dk_rd_vld}} & abr_scratch_reg.raw[mlkem_api_dk_reg_addr];
+      else if (mlkem_api_ek_reg_dec) api_reg_rdata <= {ABR_REG_WIDTH{mlkem_api_ek_rd_vld}} & abr_scratch_reg.raw[mlkem_api_ek_reg_addr];    
+      else if (api_pubkey_rho_dec)   api_reg_rdata <= {ABR_REG_WIDTH{mldsa_valid_reg}} & abr_scratch_reg.raw[api_pk_reg_raddr];
+      else if (api_sig_reg_re)       api_reg_rdata <= {ABR_REG_WIDTH{mldsa_valid_reg}} & signature_reg_rdata;
     end
   end
 

src/norm_check/rtl/norm_check_ctrl.sv

@@ -39,6 +39,7 @@ module norm_check_ctrl
         input wire [5:0] randomness,
 
         input wire [ABR_MEM_ADDR_WIDTH-1:0] mem_base_addr,
+        input logic mem_rd_data_valid,
         output mem_if_t mem_rd_req,
         output logic norm_check_done
     );
@@ -143,7 +144,7 @@ module norm_check_ctrl
                 incr_rd_addr = 1'b1;
             end
             CHK_DONE: begin
-                read_fsm_state_ns = CHK_IDLE;
+                read_fsm_state_ns = mem_rd_data_valid ? CHK_DONE: CHK_IDLE;
                 norm_check_done = 1'b1;
             end
             default begin

src/norm_check/rtl/norm_check_top.sv

@@ -54,7 +54,7 @@ module norm_check_top
     );
 
     logic [3:0] check_a_invalid;
-    logic norm_check_done_int;
+    logic norm_check_done_rd;
 
     generate 
         for (genvar i = 0; i < 4; i++) begin : gen_check_a_invalid
@@ -73,7 +73,8 @@ module norm_check_top
         else if (zeroize)
             norm_check_done <= '0;
         else
-            norm_check_done <= norm_check_done_int;
+            //signal done once reads have all been issued and processed
+            norm_check_done <= norm_check_done_rd & ~mem_rd_data_valid;
     end
 
     always_ff @(posedge clk or negedge reset_n) begin
@@ -109,7 +110,8 @@ module norm_check_top
         .randomness(randomness),
         .mem_base_addr(mem_base_addr),
         .mem_rd_req(mem_rd_req),
-        .norm_check_done(norm_check_done_int)
+        .mem_rd_data_valid(mem_rd_data_valid),
+        .norm_check_done(norm_check_done_rd)
     );
 
 

src/sk_encode/rtl/skencode.sv

@@ -61,16 +61,14 @@ module skencode
     localparam THE_LAST_ADDR = ((MLDSA_K * MLDSA_N)/4)+((MLDSA_L * MLDSA_N)/4)-1;
     localparam THE_LAST_API = ((MLDSA_K +MLDSA_L)*MLDSA_N*3)/32;
 
-    // Main State Machine States
-    localparam  SKENC_IDLE                    = 2'b00,
-                SKENC_READ                    = 2'b01,
-                SKENC_DONE                    = 2'b10;
-    
-    // Main State Machine States
-    localparam  SKENC_WAIT_BUFFER             = 2'b00,
-                SKENC_WRITE                   = 2'b01,
-                SKENC_STALL                   = 2'b10,
-                SKENC_GET_LAST                = 2'b11;
+    // State Machine States
+    localparam  SKENC_IDLE                    = 3'b000,
+                SKENC_READ                    = 3'b001,
+                SKENC_WAIT_BUFFER             = 3'b010,
+                SKENC_WRITE                   = 3'b011,
+                SKENC_STALL                   = 3'b100,
+                SKENC_GET_LAST                = 3'b101,
+                SKENC_DONE                    = 3'b111;
 
 
     logic [2:0] main_state, next_main_state, write_state, next_write_state;