update stream msg KAT to disable scoreboard and rely on self checking

update stream msg KAT to set STROBE back to 0xF at the start of each KAT

Author: Nitsirks

src/abr_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_verif_KATs_sequence.svh

@@ -97,7 +97,6 @@ class ML_DSA_verif_KATs_sequence extends mldsa_bench_sequence_base;
         ready = data[0];
       end
 
-
       // Writing the PK into the MLDSA_PUBKEY register array
       for (int j = 0; j < reg_model.MLDSA_PUBKEY.m_mem.get_size(); j++) begin
         reg_model.MLDSA_PUBKEY.m_mem.write(status, j, kat_PK[j], UVM_FRONTDOOR, reg_model.default_map, this);
@@ -157,9 +156,9 @@ class ML_DSA_verif_KATs_sequence extends mldsa_bench_sequence_base;
         end
 
         if (data !== VERIFY_RES[j]) begin
-          `uvm_error("VALIDATION_FAIL", $sformatf("SIG mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, SIG[j], data));
+          `uvm_error("VALIDATION_FAIL", $sformatf("VERIFY_RES mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, VERIFY_RES[j], data));
         end else begin
-          `uvm_info("VALIDATION_PASS", $sformatf("SIG match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW);
+          `uvm_info("VALIDATION_PASS", $sformatf("VERIFY_RES match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW);
         end
       end
 
@@ -174,7 +173,7 @@ class ML_DSA_verif_KATs_sequence extends mldsa_bench_sequence_base;
     end
 
 
-    `uvm_info("KAT", $sformatf("signing KAT validation completed"), UVM_LOW);
+    `uvm_info("KAT", $sformatf("verif KAT validation completed"), UVM_LOW);
 
 
   endtask

src/abr_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_verif_KATs_stream_msg_sequence.svh

@@ -112,16 +112,6 @@ class ML_DSA_verif_KATs_stream_msg_sequence extends mldsa_bench_sequence_base;
         end
       end
 
-      // Write MSG to MLDSA_MSG registers
-      foreach (reg_model.MLDSA_MSG[j]) begin
-        reg_model.MLDSA_MSG[j].write(status, kat_MSG[j], UVM_FRONTDOOR, reg_model.default_map, this);
-        if (status != UVM_IS_OK) begin
-          `uvm_error("REG_WRITE_FAIL", $sformatf("Failed to write MLDSA_MSG[%0d] for KAT %0d", j, i));
-        end else begin
-          `uvm_info("REG_WRITE_PASS", $sformatf("Successfully wrote MLDSA_MSG[%0d]: %h", j, kat_MSG[j]), UVM_LOW);
-        end
-      end
-
       // Writing the SIGNATURE into the MLDSA_SIGNATURE register array
       for (int j = 0; j < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); j++) begin
         reg_model.MLDSA_SIGNATURE.m_mem.write(status, j, kat_SIG[j], UVM_FRONTDOOR, reg_model.default_map, this);
@@ -151,8 +141,15 @@ class ML_DSA_verif_KATs_stream_msg_sequence extends mldsa_bench_sequence_base;
         stream_msg_rdy = data[2];
       end
 
+      //write 0 to strobe since it's aligned to trigger end
+      reg_model.MLDSA_MSG_STROBE.write(status, 4'b1111, UVM_FRONTDOOR, reg_model.default_map, this);
+      if (status != UVM_IS_OK) begin
+        `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG_STROBE"));
+      end else begin
+        `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG_STROBE written with %0h", 0), UVM_LOW);
+      end
       // Writing MLDSA_MSG register
-      // Hack to stream normal message in through streaming interface
+      // Stream message in through streaming interface
       foreach (MSG[j]) begin
         reg_model.MLDSA_MSG[0].write(status, kat_MSG[j], UVM_FRONTDOOR, reg_model.default_map, this);
         if (status != UVM_IS_OK) begin
@@ -196,9 +193,9 @@ class ML_DSA_verif_KATs_stream_msg_sequence extends mldsa_bench_sequence_base;
         end
 
         if (data !== VERIFY_RES[j]) begin
-          `uvm_error("VALIDATION_FAIL", $sformatf("SIG mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, SIG[j], data));
+          `uvm_error("VALIDATION_FAIL", $sformatf("VERIFY_RES mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, VERIFY_RES[j], data));
         end else begin
-          `uvm_info("VALIDATION_PASS", $sformatf("SIG match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW);
+          `uvm_info("VALIDATION_PASS", $sformatf("VERIFY_RES match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW);
         end
       end
 
@@ -213,7 +210,7 @@ class ML_DSA_verif_KATs_stream_msg_sequence extends mldsa_bench_sequence_base;
     end
 
 
-    `uvm_info("KAT", $sformatf("signing KAT validation completed"), UVM_LOW);
+    `uvm_info("KAT", $sformatf("verif KAT validation completed"), UVM_LOW);
 
 
   endtask

src/abr_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_verif_KATs_stream_msg_test.svh

@@ -21,6 +21,9 @@ class ML_DSA_verif_KATs_stream_msg_test extends test_top;
 
   `uvm_component_utils(ML_DSA_verif_KATs_stream_msg_test);
 
+  bit disable_scrboard_from_test;
+  bit disable_pred_from_test;
+
   function new(string name = "", uvm_component parent = null);
     super.new(name, parent);
   endfunction
@@ -33,6 +36,12 @@ class ML_DSA_verif_KATs_stream_msg_test extends test_top;
     super.build_phase(phase);
     // pragma uvmf custom configuration_settings_post_randomize begin
     // UVMF_CHANGE_ME Test specific configuration values can be set here.  
+    disable_scrboard_from_test = 1;
+    disable_pred_from_test = 1;
+
+    uvm_config_db#(bit)::set(null, "*", "disable_scrboard_from_test", disable_scrboard_from_test);
+    uvm_config_db#(bit)::set(null, "*", "disable_pred_from_test", disable_pred_from_test);
+
     // The configuration structure has already been randomized.
     // pragma uvmf custom configuration_settings_post_randomize end
   endfunction