Skip to content

Commit c4b898f

Browse files
author
Mojtaba Bisheh Niasar
committed
merged main
2 parents 53e8ace + f24a681 commit c4b898f

27 files changed

+236
-235
lines changed

‎.github/workflow_metadata/pr_hash‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
39412c9df309de283d367b9a9fcb0b41df2692f1c1521411735161a630a816e2773f95333f4b03fe653d823736bdba5b
1+
ec72e0b27630587e486ee2559c54ef26827658dbef8c7900e562dc17583b5f33ce5e83fdae864c624f6aca27318e856f

‎.github/workflow_metadata/pr_timestamp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
1765314563
1+
1765481443

‎src/abr_libs/rtl/abr_masked_A2B_conv.sv‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -53,28 +53,28 @@
5353
assign carry[0] = 2'b00;
5454

5555
// Generate the full adders for each bit
56-
genvar i;
56+
genvar g_i;
5757
generate
58-
for (i = 0; i < WIDTH; i = i + 1) begin : gen_full_adders
58+
for (g_i = 0; g_i < WIDTH; g_i = g_i + 1) begin : gen_full_adders
5959
// Pipeline registers for x and y inputs
6060
always_ff @(posedge clk or negedge rst_n) begin
6161
if (!rst_n) begin
62-
x_reg[i] <= '0;
63-
y_reg[i] <= '0;
62+
x_reg[g_i] <= '0;
63+
y_reg[g_i] <= '0;
6464
end
6565
else if (zeroize) begin
66-
x_reg[i] <= '0;
67-
y_reg[i] <= '0;
66+
x_reg[g_i] <= '0;
67+
y_reg[g_i] <= '0;
6868
end
6969
else begin
7070
for (int j = 0; j < WIDTH; j = j + 1) begin
7171
if (j == 0) begin
72-
x_reg[i][j] <= {rnd_for_Boolean0[i], (x[i][0] ^ rnd_for_Boolean0[i])};
73-
y_reg[i][j] <= {rnd_for_Boolean1[i], (x[i][1] ^ rnd_for_Boolean1[i])};
72+
x_reg[g_i][j] <= {rnd_for_Boolean0[g_i], (x[g_i][0] ^ rnd_for_Boolean0[g_i])};
73+
y_reg[g_i][j] <= {rnd_for_Boolean1[g_i], (x[g_i][1] ^ rnd_for_Boolean1[g_i])};
7474
end
7575
else begin
76-
x_reg[i][j] <= x_reg[i][j-1];
77-
y_reg[i][j] <= y_reg[i][j-1];
76+
x_reg[g_i][j] <= x_reg[g_i][j-1];
77+
y_reg[g_i][j] <= y_reg[g_i][j-1];
7878
end
7979
end
8080
end
@@ -83,37 +83,37 @@
8383
// Pipeline registers for sum output
8484
always_ff @(posedge clk or negedge rst_n) begin
8585
if (!rst_n) begin
86-
sum_reg[i] <= '0;
86+
sum_reg[g_i] <= '0;
8787
end
8888
else if (zeroize) begin
89-
sum_reg[i] <= '0;
89+
sum_reg[g_i] <= '0;
9090
end
9191
else begin
92-
for (int j = i; j < WIDTH; j = j + 1) begin
93-
if (j == i && i == WIDTH-1) begin
94-
sum_reg[i][j] <= the_last_sum;
92+
for (int j = g_i; j < WIDTH; j = j + 1) begin
93+
if (j == g_i && g_i == WIDTH-1) begin
94+
sum_reg[g_i][j] <= the_last_sum;
9595
end
96-
else if (j == i) begin
97-
sum_reg[i][j] <= sum[i];
96+
else if (j == g_i) begin
97+
sum_reg[g_i][j] <= sum[g_i];
9898
end
9999
else begin
100-
sum_reg[i][j] <= sum_reg[i][j-1];
100+
sum_reg[g_i][j] <= sum_reg[g_i][j-1];
101101
end
102102
end
103103
end
104104
end
105-
if (i<(WIDTH-1)) begin : gen_masked_full_adder
105+
if (g_i<(WIDTH-1)) begin : gen_masked_full_adder
106106
// Instance of abr_masked_full_adder
107107
abr_masked_full_adder u_abr_masked_full_adder (
108108
.clk(clk), // Connect clk to clk
109109
.rst_n(rst_n), // Connect rst_n to rst_n
110110
.zeroize(zeroize), // Connect zeroize to zeroize
111-
.x(x_reg[i][i]), // Connect x to the last stage of the x pipeline
112-
.y(y_reg[i][i]), // Connect y to the last stage of the y pipeline
113-
.c_in(carry[i]), // Connect c_in to carry[i]
114-
.rnd(rnd[i]), // Connect rnd to corresponding random bit
115-
.s(sum[i]), // Connect sum to sum[i]
116-
.c_out(carry[i+1]) // Connect carry out to carry[i+1]
111+
.x(x_reg[g_i][g_i]), // Connect x to the last stage of the x pipeline
112+
.y(y_reg[g_i][g_i]), // Connect y to the last stage of the y pipeline
113+
.c_in(carry[g_i]), // Connect c_in to carry[g_i]
114+
.rnd(rnd[g_i]), // Connect rnd to corresponding random bit
115+
.s(sum[g_i]), // Connect sum to sum[g_i]
116+
.c_out(carry[g_i+1]) // Connect carry out to carry[g_i+1]
117117
);
118118
end
119119
end

‎src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -51,28 +51,28 @@
5151
assign carry[0] = 2'b00;
5252

5353
// Generate the full adders for each bit
54-
genvar i;
54+
genvar g_i;
5555
generate
56-
for (i = 0; i < WIDTH; i = i + 1) begin : gen_full_adders
56+
for (g_i = 0; g_i < WIDTH; g_i = g_i + 1) begin : gen_full_adders
5757
// Pipeline registers for x and y inputs
5858
always_ff @(posedge clk or negedge rst_n) begin
5959
if (!rst_n) begin
60-
x_reg[i] <= '0;
61-
y_reg[i] <= '0;
60+
x_reg[g_i] <= '0;
61+
y_reg[g_i] <= '0;
6262
end
6363
else if (zeroize) begin
64-
x_reg[i] <= '0;
65-
y_reg[i] <= '0;
64+
x_reg[g_i] <= '0;
65+
y_reg[g_i] <= '0;
6666
end
6767
else begin
6868
for (int j = 0; j < WIDTH; j = j + 1) begin
6969
if (j == 0) begin
70-
x_reg[i][j] <= x[i];
71-
y_reg[i][j] <= y[i];
70+
x_reg[g_i][j] <= x[g_i];
71+
y_reg[g_i][j] <= y[g_i];
7272
end
7373
else begin
74-
x_reg[i][j] <= x_reg[i][j-1];
75-
y_reg[i][j] <= y_reg[i][j-1];
74+
x_reg[g_i][j] <= x_reg[g_i][j-1];
75+
y_reg[g_i][j] <= y_reg[g_i][j-1];
7676
end
7777
end
7878
end
@@ -81,37 +81,37 @@
8181
// Pipeline registers for sum output
8282
always_ff @(posedge clk or negedge rst_n) begin
8383
if (!rst_n) begin
84-
sum_reg[i] <= '0;
84+
sum_reg[g_i] <= '0;
8585
end
8686
else if (zeroize) begin
87-
sum_reg[i] <= '0;
87+
sum_reg[g_i] <= '0;
8888
end
8989
else begin
90-
for (int j = i; j < WIDTH; j = j + 1) begin
91-
if (j == i && i == WIDTH-1) begin
92-
sum_reg[i][j] <= the_last_sum;
90+
for (int j = g_i; j < WIDTH; j = j + 1) begin
91+
if (j == g_i && g_i == WIDTH-1) begin
92+
sum_reg[g_i][j] <= the_last_sum;
9393
end
94-
else if (j == i) begin
95-
sum_reg[i][j] <= sum[i];
94+
else if (j == g_i) begin
95+
sum_reg[g_i][j] <= sum[g_i];
9696
end
9797
else begin
98-
sum_reg[i][j] <= sum_reg[i][j-1];
98+
sum_reg[g_i][j] <= sum_reg[g_i][j-1];
9999
end
100100
end
101101
end
102102
end
103-
if (i<(WIDTH-1)) begin : gen_masked_full_adder
103+
if (g_i<(WIDTH-1)) begin : gen_masked_full_adder
104104
// Instance of abr_masked_full_adder
105105
abr_masked_full_adder u_abr_masked_full_adder (
106106
.clk(clk), // Connect clk to clk
107107
.rst_n(rst_n), // Connect rst_n to rst_n
108108
.zeroize(zeroize), // Connect zeroize to zeroize
109-
.x(x_reg[i][i]), // Connect x to the last stage of the x pipeline
110-
.y(y_reg[i][i]), // Connect y to the last stage of the y pipeline
111-
.c_in(carry[i]), // Connect c_in to carry[i]
112-
.rnd(rnd[i]), // Connect rnd to corresponding random bit
113-
.s(sum[i]), // Connect sum to sum[i]
114-
.c_out(carry[i+1]) // Connect carry out to carry[i+1]
109+
.x(x_reg[g_i][g_i]), // Connect x to the last stage of the x pipeline
110+
.y(y_reg[g_i][g_i]), // Connect y to the last stage of the y pipeline
111+
.c_in(carry[g_i]), // Connect c_in to carry[g_i]
112+
.rnd(rnd[g_i]), // Connect rnd to corresponding random bit
113+
.s(sum[g_i]), // Connect sum to sum[g_i]
114+
.c_out(carry[g_i+1]) // Connect carry out to carry[g_i+1]
115115
);
116116
end
117117
end

‎src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -45,28 +45,28 @@ module abr_masked_N_bit_Boolean_sub #(
4545
assign carry[0] = sub_i ? 2'b01 : 2'b00;
4646

4747
// Generate the full adders for each bit
48-
genvar i;
48+
genvar g_i;
4949
generate
50-
for (i = 0; i < WIDTH; i = i + 1) begin : gen_full_adders
50+
for (g_i = 0; g_i < WIDTH; g_i = g_i + 1) begin : gen_full_adders
5151
// Pipeline registers for x and y inputs
5252
always_ff @(posedge clk or negedge rst_n) begin
5353
if (!rst_n) begin
54-
x_reg[i] <= '0;
55-
y_reg[i] <= '0;
54+
x_reg[g_i] <= '0;
55+
y_reg[g_i] <= '0;
5656
end
5757
else if (zeroize) begin
58-
x_reg[i] <= '0;
59-
y_reg[i] <= '0;
58+
x_reg[g_i] <= '0;
59+
y_reg[g_i] <= '0;
6060
end
6161
else begin
6262
for (int j = 0; j < WIDTH; j = j + 1) begin
6363
if (j == 0) begin
64-
x_reg[i][j] <= x[i];
65-
y_reg[i][j] <= y[i];
64+
x_reg[g_i][j] <= x[g_i];
65+
y_reg[g_i][j] <= y[g_i];
6666
end
6767
else begin
68-
x_reg[i][j] <= x_reg[i][j-1];
69-
y_reg[i][j] <= y_reg[i][j-1];
68+
x_reg[g_i][j] <= x_reg[g_i][j-1];
69+
y_reg[g_i][j] <= y_reg[g_i][j-1];
7070
end
7171
end
7272
end
@@ -75,37 +75,37 @@ module abr_masked_N_bit_Boolean_sub #(
7575
// Pipeline registers for sum output
7676
always_ff @(posedge clk or negedge rst_n) begin
7777
if (!rst_n) begin
78-
sum_reg[i] <= '0;
78+
sum_reg[g_i] <= '0;
7979
end
8080
else if (zeroize) begin
81-
sum_reg[i] <= '0;
81+
sum_reg[g_i] <= '0;
8282
end
8383
else begin
84-
for (int j = i; j < WIDTH; j = j + 1) begin
85-
if (j == i && i == WIDTH-1) begin
86-
sum_reg[i][j] <= the_last_sum;
84+
for (int j = g_i; j < WIDTH; j = j + 1) begin
85+
if (j == g_i && g_i == WIDTH-1) begin
86+
sum_reg[g_i][j] <= the_last_sum;
8787
end
88-
else if (j == i) begin
89-
sum_reg[i][j] <= sum[i];
88+
else if (j == g_i) begin
89+
sum_reg[g_i][j] <= sum[g_i];
9090
end
9191
else begin
92-
sum_reg[i][j] <= sum_reg[i][j-1];
92+
sum_reg[g_i][j] <= sum_reg[g_i][j-1];
9393
end
9494
end
9595
end
9696
end
97-
if (i<(WIDTH-1)) begin : gen_masked_full_adder
97+
if (g_i<(WIDTH-1)) begin : gen_masked_full_adder
9898
// Instance of abr_masked_full_adder
9999
abr_masked_full_adder u_abr_masked_full_adder (
100100
.clk(clk), // Connect clk to clk
101101
.rst_n(rst_n), // Connect rst_n to rst_n
102102
.zeroize(zeroize), // Connect zeroize to zeroize
103-
.x(x_reg[i][i]), // Connect x to the last stage of the x pipeline
104-
.y(y_reg[i][i]), // Connect y to the last stage of the y pipeline
105-
.c_in(carry[i]), // Connect c_in to carry[i]
106-
.rnd(rnd[i]), // Connect rnd to corresponding random bit
107-
.s(sum[i]), // Connect sum to sum[i]
108-
.c_out(carry[i+1]) // Connect carry out to carry[i+1]
103+
.x(x_reg[g_i][g_i]), // Connect x to the last stage of the x pipeline
104+
.y(y_reg[g_i][g_i]), // Connect y to the last stage of the y pipeline
105+
.c_in(carry[g_i]), // Connect c_in to carry[g_i]
106+
.rnd(rnd[g_i]), // Connect rnd to corresponding random bit
107+
.s(sum[g_i]), // Connect sum to sum[g_i]
108+
.c_out(carry[g_i+1]) // Connect carry out to carry[g_i+1]
109109
);
110110
end
111111
end

‎src/abr_libs/rtl/abr_piso_multi.sv‎

Lines changed: 18 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,15 @@ module abr_piso_multi #(
3939

4040
logic [PISO_BUFFER_W-1:0] buffer, buffer_d;
4141
logic [PISO_PTR_W-1:0] buffer_wr_ptr, buffer_wr_ptr_d;
42+
logic [PISO_PTR_W-1:0] buffer_rw_ptr;
4243
logic [PISO_PTR_W-1:0] current_input_rate, current_output_rate;
4344

45+
logic wr_ptr_overflow;
46+
47+
// Write data and mask
48+
logic [PISO_BUFFER_W-1:0] buffer_wdata;
49+
logic [PISO_BUFFER_W-1:0] buffer_wdata_mask;
50+
4451
logic buffer_wr, buffer_rd;
4552
logic update_buffer;
4653

@@ -51,8 +58,8 @@ module abr_piso_multi #(
5158
end
5259

5360
// Flow control
54-
always_comb hold_o = buffer_rd ? buffer_wr_ptr > (PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate + current_output_rate) :
55-
buffer_wr_ptr > (PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate);
61+
always_comb hold_o = buffer_rd ? buffer_wr_ptr > PISO_PTR_W'(PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate + current_output_rate):
62+
buffer_wr_ptr > PISO_PTR_W'(PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate);
5663
always_comb data_o = buffer[PISO_ACT_OUTPUT_RATE-1:0];
5764
always_comb valid_o = buffer_wr_ptr >= current_output_rate;
5865

@@ -76,18 +83,18 @@ module abr_piso_multi #(
7683

7784
// Write pointer control
7885
always_comb begin
86+
wr_ptr_overflow = 1'b0;
7987
unique case ({buffer_rd, buffer_wr})
8088
2'b00 : buffer_wr_ptr_d = buffer_wr_ptr;
81-
2'b01 : buffer_wr_ptr_d = buffer_wr_ptr + current_input_rate;
82-
2'b10 : buffer_wr_ptr_d = buffer_wr_ptr - current_output_rate;
83-
2'b11 : buffer_wr_ptr_d = buffer_wr_ptr + (current_input_rate - current_output_rate);
89+
2'b01 : {wr_ptr_overflow, buffer_wr_ptr_d} = buffer_wr_ptr + current_input_rate;
90+
2'b10 : {wr_ptr_overflow, buffer_wr_ptr_d} = buffer_wr_ptr - current_output_rate;
91+
2'b11 : {wr_ptr_overflow, buffer_wr_ptr_d} = buffer_wr_ptr + (current_input_rate - current_output_rate);
8492
default : buffer_wr_ptr_d = buffer_wr_ptr;
8593
endcase
8694
end
8795

88-
// Write data and mask
89-
logic [PISO_BUFFER_W-1:0] buffer_wdata;
90-
logic [PISO_BUFFER_W-1:0] buffer_wdata_mask;
96+
// Calculate the write point for rw cases
97+
always_comb buffer_rw_ptr = buffer_wr_ptr - current_output_rate;
9198

9299
always_comb begin
93100
buffer_wdata = '0;
@@ -102,10 +109,12 @@ module abr_piso_multi #(
102109
2'b00 : buffer_d = buffer;
103110
2'b10 : buffer_d = PISO_BUFFER_W'(buffer >> current_output_rate);
104111
2'b01 : buffer_d = PISO_BUFFER_W'(buffer_wdata << buffer_wr_ptr) | buffer;
105-
2'b11 : buffer_d = PISO_BUFFER_W'(buffer_wdata << (buffer_wr_ptr - current_output_rate)) |
112+
2'b11 : buffer_d = PISO_BUFFER_W'(buffer_wdata << (buffer_rw_ptr)) |
106113
PISO_BUFFER_W'(buffer >> current_output_rate);
107114
default : buffer_d = buffer;
108115
endcase
109116
end
110117

118+
`ABR_ASSERT_NEVER(ABR_PISO_MULTI_WR_PTR_OVERFLOW, wr_ptr_overflow, clk, !rst_b)
119+
111120
endmodule

‎src/abr_libs/rtl/abr_rd_lat_buffer.sv‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ module abr_rd_lat_buffer
4747
//Buffer
4848
logic [BUFFER_DEPTH-1:0] buffer, buffer_d, buffer_shift, buffer_wr_data_shift;
4949
logic [$clog2(BUFFER_DEPTH):0] wr_ptr, wr_ptr_d;
50+
logic [$clog2(BUFFER_DEPTH):0] rw_ptr;
5051

5152
//Read when we have NUM_RD worth of valid data
5253
always_comb buffer_rd = wr_ptr >= RD_WIDTH;
@@ -67,10 +68,12 @@ module abr_rd_lat_buffer
6768
wr_ptr_d = wr_ptr;
6869
end
6970

71+
always_comb rw_ptr = (wr_ptr - RD_WIDTH);
72+
7073
//Shift the buffer contents and append new samples
7174
always_comb begin
7275
//shift the write data left by the wr_ptr, or wr_ptr - RD_WIDTH if there is a read
73-
buffer_wr_data_shift = buffer_wr & buffer_rd ? BUFFER_DEPTH'(data_i << (wr_ptr - RD_WIDTH)) :
76+
buffer_wr_data_shift = buffer_wr & buffer_rd ? BUFFER_DEPTH'(data_i << rw_ptr) :
7477
buffer_wr ? BUFFER_DEPTH'(data_i << wr_ptr) : '0;
7578

7679
//shift the buffer data right by NUM_RD if there is a read

‎src/abr_sampler_top/rtl/abr_sampler_top.sv‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -280,8 +280,11 @@ module abr_sampler_top
280280
zeroize_piso |= sampler_done;
281281
piso_mode = ABR_CBD_MODE;
282282
end
283+
ABR_SAMPLER_NONE: begin
284+
//do nothing
285+
end
283286
default: begin
284-
287+
//do nothing
285288
end
286289
endcase
287290
end

‎src/abr_sha3/rtl/abr_sha3.sv‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -356,7 +356,12 @@ module abr_sha3
356356
end
357357
end
358358

359+
StTerminalError_sparse: begin
360+
// Do nothing
361+
end
362+
359363
default: begin
364+
// Do nothing
360365
end
361366
endcase
362367
end

0 commit comments

Comments
 (0)