[DOC] Clarify min clock frequency requirement (#1011)

* Update clock frequency requirements in specification

Clarified minimum operating clock frequency requirements for I3C core.

* Correct timing reference in clock frequency section

Author: clayton8

docs/CaliptraSSIntegrationSpecification.md

@@ -500,6 +500,7 @@ The `cptra_ss_clk_i` signal is the primary clock input for the Caliptra Subsyste
   - **Signal Name** `cptra_ss_clk_i`
   - **Required Frequency** 333* MHz to 400 MHz
     - I3C core imposes requirement for minimum operating clock frequency set to 333 MHz or higher to meet 12ns tSCO timing.
+      - 333 MHz was calculated assuming SCL PAD -> D and SDA Q -> PAD timing is 0. SOCs with large timing delays might need to run at a faster clock frequency to meet tSCO timing of 12ns. 
     - SoCs that run Caliptra lower than 333 MHz will limit the max I3C SCL frequency. See [I3C Phy Spec](https://chipsalliance.github.io/i3c-core/phy.html#clock-synchronization-5-1-7) for more details.
     - This was changed from 170 MHz floor due to CDC issue found in I3C core:
        - [I3C Repo CDC Issue](https://github.com/chipsalliance/i3c-core/issues/72)