[2.1] MLDSA KAT Fail on FPGA

[RaunakGu]

MLDSA KAT fails on FPGA,
@mtimkovich could you please check if this is an open issue?

branch - caliptra-2.1-dev
WG MCU commit: f21c8720e554cc38f7ccfbed63c06ef502203287
WG SW commit: c43fc06

[clundin25]

@RaunakGu caliptra-2.1-dev has migrated to main. Can you confirm if you have the same issue on main?

[RaunakGu]

@clundin25 ,
Apologies, mentioned commit is already from main, not from caliptra-2.1-dev

Caliptra-SW: c43fc06b9

[clundin25]

@RaunakGu I don't see any ML-DSA KAT failures in the latest nightly run: https://github.com/chipsalliance/caliptra-sw/actions/runs/20675948419

Can you clarify whether the bitstream you are testing with is based on the RTL used in CI?

https://github.com/chipsalliance/caliptra-sw/blob/main/hw/fpga/bitstream_manifests/subsystem.toml

[RaunakGu]

Thanks @clundin25,
Yeah it is the same RTL reference,

Update: Seems our design team has already looking into this issue, and it looks like SRAM latency issue causing MLDSA Keygen failures, below is the filed issue reference
chipsalliance/adams-bridge#243

[clundin25]

@RaunakGu thanks for the update. Is this resolved then? If it's a hardware issue it may be appropriate to migrate the discussion to the relevant hardware repo.

[RaunakGu]

I will close it here for now, thank you