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Use README.rst instead of README.md
Signed-off-by: Daniel Lim Wee Soong <[email protected]>
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README.md

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README.rst

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SymbiFlow Verilog to VtR XML (v2x)
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===================================
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.. image:: https://readthedocs.org/projects/python-symbiflow-v2x/badge/?version=latest
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:target: https://python-symbiflow-v2x.readthedocs.io/en/latest/?badge=latest
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:alt: Documentation Status
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.. image:: https://travis-ci.com/SymbiFlow/python-symbiflow-v2x.svg?branch=master
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:target: https://travis-ci.com/SymbiFlow/python-symbiflow-v2x
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:alt: Build Status
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v2x is a tool for converting specialized annotated Verilog models into XML needed for
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`Verilog to Routing flow <https://docs.verilogtorouting.org/en/latest/arch/reference/>`_.
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Documentation can be found at `https://python-symbiflow-v2x.readthedocs.io/en/latest/ <https://python-symbiflow-v2x.readthedocs.io/en/latest/examples.html>`_.
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Installation
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------------
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v2x can be installed from a local git repository using pip.
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.. code-block::
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cd python-symbiflow-v2x
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pip install .
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Alternatively, it can be installed from GitHub directly.
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.. code-block::
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pip install git+https://github.com/SymbiFlow/python-symbiflow-v2x.git#egg=python-symbiflow-v2x
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Usage
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-----
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After installing v2x, you can run ``python -m v2x`` to use it.
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.. code-block::
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python -m v2x -h
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usage: __main__.py [-h] [--top TOP] [--outfile OUTFILE] [--includes INCLUDES]
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[--mode {pb_type,model}]
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input.v [input.v ...]
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Verilog to XML
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positional arguments:
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input.v One or more Verilog input files, that will be passed
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to Yosys internally. They should be enough to generate
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a flattened representation of the model, so that paths
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through the model can be determined.
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optional arguments:
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-h, --help show this help message and exit
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--top TOP Top level module, will usually be automatically
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determined from the file name im.v
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--outfile OUTFILE, -o OUTFILE
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Output filename, default 'output.xml'
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--includes INCLUDES Comma separate list of include directories.
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--mode {pb_type,model}
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Output file type, possible values are: pb_type and
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model. Default value is pb_type
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For example, to generate a pb_type xml file from adder.v, run
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.. code-block::
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python -m v2x -o adder.pb_type.xml adder.v
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Or, to generate a model xml file, run
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.. code-block::
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python -m v2x --mode model -o adder.model.xml adder.v
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v2x expects the module name to be the same as the file name. If it is different, make sure to specifiy it with the ``--top`` argument.
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.. code-block::
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python -m v2x --top BLOCK -o adder.pb_type.xml adder.v
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Tests
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-----
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The test cases are stored in tests/, and pytest can be used to run them.
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.. code-block::
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rm -rf build # run this step so that pytest uses the latest files for the tests
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pytest -vv
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If you are making changes to any python code, make sure that they follow the PEP8 style guide by running flake8.
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.. code-block::
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flake8 tests
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flake8 v2x
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Documentation
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-------------
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We use sphinx for our documentation and the files are stored in docs/. To host it locally (if you are planning to update it), you can use the Makefile inside.
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First, run ``make env`` to prepare a Conda environment that contains the necessary packages to build and host the documentation site. After that, simply run ``make livehtml`` which starts a local server running at port 8000 with the documentation site.
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.. code-block::
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cd docs
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make env
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make livehtml
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Talks
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-----
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**VPR device models generation from Verilog with V2X - Karol Gugala - ORConf 2019**
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.. image:: https://img.youtube.com/vi/a31vH_tZLBM/0.jpg
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:target: https://www.youtube.com/watch?v=a31vH_tZLBM
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:alt: v2x orconf talk
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docs/conf.py

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'sphinx.ext.todo',
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'sphinx_markdown_tables',
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'symbolator_sphinx',
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'sphinxcontrib_verilog_diagrams',
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'm2r'
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'sphinxcontrib_verilog_diagrams'
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]
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# Add any paths that contain templates here, relative to this directory.
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# The suffix(es) of source filenames.
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# You can specify multiple suffix as a list of string:
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source_suffix = ['.rst', '.md']
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source_parsers = {
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'.md': 'markdown_code_symlinks.LinkParser',
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}
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# The master toctree document.
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master_doc = 'index'

docs/index.rst

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.. mdinclude:: ../README.md
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.. include:: ../README.rst
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.. toctree::
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introduction.rst

docs/requirements.txt

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# Verilog diagrams using Yosys + netlistsvg
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git+https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams.git#egg=sphinxcontrib-verilog-diagrams
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git+https://github.com/daniellimws/m2r.git#egg=m2r
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# Module diagrams
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symbolator

setup.py

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import setuptools
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with open("README.md", "r") as fh:
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with open("README.rst", "r") as fh:
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long_description = fh.read()
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setuptools.setup(

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