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| 1 | +From 7c93699a9c0002d110aec5c62843084ece7403ba Mon Sep 17 00:00:00 2001 |
| 2 | +From: Kamil Rakoczy <krakoczy@antmicro.com> |
| 3 | +Date: Wed, 26 Apr 2023 15:04:59 +0200 |
| 4 | +Subject: [PATCH 3/4] WIP: Replace stream operator without reverse |
| 5 | + |
| 6 | +Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> |
| 7 | +--- |
| 8 | + bp_me/src/v/cce/bp_cce_dir_segment.sv | 2 +- |
| 9 | + bp_me/src/v/cce/bp_cce_pending_bits.sv | 4 ++-- |
| 10 | + bp_me/src/v/cce/bp_cce_spec_bits.sv | 4 ++-- |
| 11 | + bp_me/src/v/network/bp_me_addr_to_cce_id.sv | 2 +- |
| 12 | + bp_top/test/common/bp_nonsynth_host.sv | 2 +- |
| 13 | + 5 files changed, 7 insertions(+), 7 deletions(-) |
| 14 | + |
| 15 | +diff --git a/bp_me/src/v/cce/bp_cce_dir_segment.sv b/bp_me/src/v/cce/bp_cce_dir_segment.sv |
| 16 | +index 94abc422..20394392 100644 |
| 17 | +--- a/bp_me/src/v/cce/bp_cce_dir_segment.sv |
| 18 | ++++ b/bp_me/src/v/cce/bp_cce_dir_segment.sv |
| 19 | +@@ -126,7 +126,7 @@ module bp_cce_dir_segment |
| 20 | + logic [lg_num_cce_lp-1:0] cce_id_lo; |
| 21 | + logic [hash_index_width_lp-1:0] set_id_lo; |
| 22 | + // NOTE: reverse the address to use the low order bits for striping cache blocks across CCEs |
| 23 | +- wire [lg_sets_lp-1:0] hash_addr_rev = { <<{addr_i[lg_block_size_in_bytes_lp+:lg_sets_lp]}}; |
| 24 | ++ wire [lg_sets_lp-1:0] hash_addr_rev = addr_i[lg_block_size_in_bytes_lp+:lg_sets_lp]; // TODO: reverse order |
| 25 | + |
| 26 | + bsg_hash_bank |
| 27 | + #(.banks_p(num_cce_p) // number of CCE's to spread way groups over |
| 28 | +diff --git a/bp_me/src/v/cce/bp_cce_pending_bits.sv b/bp_me/src/v/cce/bp_cce_pending_bits.sv |
| 29 | +index 517c79df..94edd948 100644 |
| 30 | +--- a/bp_me/src/v/cce/bp_cce_pending_bits.sv |
| 31 | ++++ b/bp_me/src/v/cce/bp_cce_pending_bits.sv |
| 32 | +@@ -62,8 +62,8 @@ module bp_cce_pending_bits |
| 33 | + // Address to way group hashing |
| 34 | + // The address to use as input starts at addr_offset_p and is lg_cce_way_groups_lp bits in length |
| 35 | + logic [hash_idx_width_lp-1:0] r_wg_lo, w_wg_lo; |
| 36 | +- wire [lg_cce_way_groups_lp-1:0] r_addr_rev = {<< {r_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; |
| 37 | +- wire [lg_cce_way_groups_lp-1:0] w_addr_rev = {<< {w_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; |
| 38 | ++ wire [lg_cce_way_groups_lp-1:0] r_addr_rev = r_addr_i[addr_offset_p+:lg_cce_way_groups_lp];// TODO: reverse order |
| 39 | ++ wire [lg_cce_way_groups_lp-1:0] w_addr_rev = w_addr_i[addr_offset_p+:lg_cce_way_groups_lp];// TODO: reverse order |
| 40 | + logic [lg_num_way_groups_lp-1:0] r_wg, w_wg; |
| 41 | + |
| 42 | + bsg_hash_bank |
| 43 | +diff --git a/bp_me/src/v/cce/bp_cce_spec_bits.sv b/bp_me/src/v/cce/bp_cce_spec_bits.sv |
| 44 | +index c0b87884..f6523067 100644 |
| 45 | +--- a/bp_me/src/v/cce/bp_cce_spec_bits.sv |
| 46 | ++++ b/bp_me/src/v/cce/bp_cce_spec_bits.sv |
| 47 | +@@ -58,8 +58,8 @@ module bp_cce_spec_bits |
| 48 | + |
| 49 | + // Address to way group hashing |
| 50 | + logic [hash_idx_width_lp-1:0] r_wg_lo, w_wg_lo; |
| 51 | +- wire [lg_cce_way_groups_lp-1:0] r_addr_rev = {<< {r_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; |
| 52 | +- wire [lg_cce_way_groups_lp-1:0] w_addr_rev = {<< {w_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; |
| 53 | ++ wire [lg_cce_way_groups_lp-1:0] r_addr_rev = r_addr_i[addr_offset_p+:lg_cce_way_groups_lp];// TODO: reverse order |
| 54 | ++ wire [lg_cce_way_groups_lp-1:0] w_addr_rev = w_addr_i[addr_offset_p+:lg_cce_way_groups_lp];// TODO: reverse order |
| 55 | + logic [lg_num_way_groups_lp-1:0] r_wg, w_wg; |
| 56 | + |
| 57 | + bsg_hash_bank |
| 58 | +diff --git a/bp_me/src/v/network/bp_me_addr_to_cce_id.sv b/bp_me/src/v/network/bp_me_addr_to_cce_id.sv |
| 59 | +index d3100ed4..b8cd9e76 100644 |
| 60 | +--- a/bp_me/src/v/network/bp_me_addr_to_cce_id.sv |
| 61 | ++++ b/bp_me/src/v/network/bp_me_addr_to_cce_id.sv |
| 62 | +@@ -48,7 +48,7 @@ module bp_me_addr_to_cce_id |
| 63 | + // at the cache block granularity |
| 64 | + logic [lce_sets_width_p-1:0] hash_addr_li; |
| 65 | + logic [lg_num_cce_lp-1:0] cce_dst_id_lo; |
| 66 | +- assign hash_addr_li = {<< {paddr_i[block_offset_lp+:lce_sets_width_p]}}; |
| 67 | ++ assign hash_addr_li = paddr_i[block_offset_lp+:lce_sets_width_p]; //TODO: reverse order |
| 68 | + bsg_hash_bank |
| 69 | + #(.banks_p(num_cce_p) // number of CCE's to spread way groups over |
| 70 | + ,.width_p(lce_sets_width_p) // width of address input |
| 71 | +diff --git a/bp_top/test/common/bp_nonsynth_host.sv b/bp_top/test/common/bp_nonsynth_host.sv |
| 72 | +index 16dd997f..e62db586 100644 |
| 73 | +--- a/bp_top/test/common/bp_nonsynth_host.sv |
| 74 | ++++ b/bp_top/test/common/bp_nonsynth_host.sv |
| 75 | +@@ -204,7 +204,7 @@ module bp_nonsynth_host |
| 76 | + ); |
| 77 | + |
| 78 | + // Convert to little endian |
| 79 | +- wire [dword_width_gp-1:0] bootrom_data_reverse = {<<8{bootrom_data_lo}}; |
| 80 | ++ wire [dword_width_gp-1:0] bootrom_data_reverse = bootrom_data_lo; // TODO: reverse order |
| 81 | + |
| 82 | + logic [dword_width_gp-1:0] bootrom_final_lo; |
| 83 | + bsg_bus_pack |
| 84 | +-- |
| 85 | +2.39.0 |
| 86 | + |
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