Force installation of lower simplesat version (#2543)

This addresses broken simplesat v0.9.0 wheel.

Co-authored-by: mszelwiga <mszelwiga@internships.antmicro.com>

Author: kamilrakoczy

tests/ibex/Makefile.in

@@ -13,6 +13,8 @@ uhdm/synlig/synth-ibex: clean-build ${IBEX}/.gitpatch
 	virtualenv ${root_dir}/venv-ibex
 	(export PATH=${OUT_DIR}/bin:${PATH} && \
 		. ${root_dir}/venv-ibex/bin/activate && \
+		# https://github.com/enthought/sat-solver/issues/286 \
+		pip install git+https://github.com/enthought/sat-solver.git@v0.8.2 && \
 		pip install -r ${IBEX}/python-requirements.txt && \
 		pip install git+https://github.com/antmicro/edalize@svplugin_support && \
 		fusesoc --cores-root=${IBEX} run --build --tool synlig --target=synth lowrisc:ibex:top_artya7_surelog --SRAMInitFile="${curr_dir}/led.vmem")
@@ -21,6 +23,8 @@ uhdm/synlig/synth-ibex-build: clean-build ${IBEX}/.gitpatch
 	virtualenv ${root_dir}/venv-ibex
 	(export PATH=${OUT_DIR}/bin:${PATH} && \
 		. ${root_dir}/venv-ibex/bin/activate && \
+		# https://github.com/enthought/sat-solver/issues/286 \
+		pip install git+https://github.com/enthought/sat-solver.git@v0.8.2 && \
 		pip install -r ${IBEX}/python-requirements.txt && \
 		pip install git+https://github.com/antmicro/edalize@svplugin_support && \
 		fusesoc --cores-root=${IBEX} run --build --tool vivado --target=synth lowrisc:ibex:top_artya7_surelog --part xc7a35ticsg324-1L --SRAMInitFile="${curr_dir}/led.vmem")
@@ -78,6 +82,8 @@ ${REQUIREMENTS_FILE}: ${IBEX}/.requirementspatch
 # Install conda packages from f4pga/xc7 environment and set environment variables.
 env:: download-f4pga install-plugins
 	${IN_CONDA_ENV} conda env update --name ${CONDA_ENV_NAME} --file ${root_dir}/env/f4pga/xc7_env/xc7_environment.yml </dev/null | cat
+	# https://github.com/enthought/sat-solver/issues/286
+	${IN_CONDA_ENV} pip install -I git+https://github.com/enthought/sat-solver.git@v0.8.2
 	# Update edalize installed by Ibex to our own fork.
 	${IN_CONDA_ENV} pip install \
 		git+https://github.com/antmicro/edalize@symbiflow-read_verilog_with_uhdm \

tests/opentitan/Makefile.in

@@ -12,6 +12,8 @@ ${OPENTITAN_9d82960888}/.gitpatch:
 ${VENV_OT_9d82960888}:
 	virtualenv ${VENV_OT_9d82960888}
 	. ${VENV_OT_9d82960888}/bin/activate && \
+	# https://github.com/enthought/sat-solver/issues/286 \
+	pip install -I git+https://github.com/enthought/sat-solver.git@v0.8.2 && \
 	pip install -r ${OPENTITAN_9d82960888}/python-requirements.txt && \
 	pip install git+https://github.com/antmicro/edalize@svplugin_support
 
@@ -42,6 +44,8 @@ ${OPENTITAN}/.gitpatch_synth:
 ${VENV_OT_SYNTH}: | ${OPENTITAN}/.gitpatch_synth
 	virtualenv ${VENV_OT_SYNTH}
 	(. ${VENV_OT_SYNTH}/bin/activate && \
+		# https://github.com/enthought/sat-solver/issues/286 \
+		pip install -I git+https://github.com/enthought/sat-solver.git@v0.8.2 && \
 		pip install -r ${OPENTITAN}/python-requirements.txt && \
 		pip install git+https://github.com/antmicro/edalize@svplugin_support)
 

tests/opentitan/opentitan_parsing_test/Makefile

@@ -169,6 +169,8 @@ env: ${VENV_DIR}
 ${VENV_DIR} : | ${BUILD_DIR}
 	virtualenv ${VENV_DIR}
 	. ${VENV_DIR}/bin/activate
+	# https://github.com/enthought/sat-solver/issues/286
+	pip install -I git+https://github.com/enthought/sat-solver.git@v0.8.2
 	pip install -r ${OPENTITAN_DIR}/python-requirements.txt
 	pip install pygraphviz
 	(

tests/veer/Makefile.in

@@ -15,20 +15,26 @@ uhdm/synlig/veer: clean-build | ${VENV} ${DESIGN_DIR}/.gitpatch
 	(export PATH=${OUT_DIR}/bin:${PATH} && \
 		. ${VENV}/bin/activate && \
 		pip install -I git+https://github.com/antmicro/edalize@svplugin_support && \
+		# https://github.com/enthought/sat-solver/issues/286 \
+		pip install -I git+https://github.com/enthought/sat-solver.git@v0.8.2 && \
 		pip install git+https://github.com/lowRISC/fusesoc.git@ot && \
 		fusesoc --cores-root=${DESIGN_DIR} run --build --tool synlig --target=synth chipsalliance.org:cores:VeeR_EH1:1.8)
 
 uhdm/synlig/veer-build: clean-build | ${VENV} ${DESIGN_DIR}/.gitpatch
 	(export PATH=${OUT_DIR}/bin:${PATH} && \
 		. ${VENV}/bin/activate && \
 		pip install -I git+https://github.com/antmicro/edalize@svplugin_support && \
+		# https://github.com/enthought/sat-solver/issues/286 \
+		pip install -I git+https://github.com/enthought/sat-solver.git@v0.8.2 && \
 		pip install git+https://github.com/lowRISC/fusesoc.git@ot && \
 		fusesoc --cores-root=${DESIGN_DIR} run --build --tool vivado --target=synth chipsalliance.org:cores:VeeR_EH1:1.8)
 
 uhdm/sv2v/veer: clean-build | ${VENV}
 	(export PATH=${OUT_DIR}/bin:${PATH} && \
 		. ${VENV}/bin/activate && \
 		pip install -I git+https://github.com/antmicro/edalize@svplugin_support && \
+		# https://github.com/enthought/sat-solver/issues/286 \
+		pip install -I git+https://github.com/enthought/sat-solver.git@v0.8.2 && \
 		pip install git+https://github.com/lowRISC/fusesoc.git@ot && \
 		fusesoc --cores-root=${DESIGN_DIR} run --build --tool sv2v --target=synth chipsalliance.org:cores:VeeR_EH1:1.8)