Device Tree Support

backends/igvm.c

@@ -26,6 +26,9 @@
 #include <igvm/igvm.h>
 #include <igvm/igvm_defs.h>
 
+#ifdef CONFIG_FDT
+#include <libfdt.h>
+#endif
 
 /*
  * Some directives are specific to particular confidential computing platforms.
@@ -100,6 +103,10 @@ static int qigvm_directive_snp_id_block(QIgvm *ctx, const uint8_t *header_data,
 static int qigvm_initialization_guest_policy(QIgvm *ctx,
                                        const uint8_t *header_data,
                                        Error **errp);
+#ifdef CONFIG_FDT
+static int qigvm_directive_device_tree(QIgvm *ctx, const uint8_t *header_data,
+                                       Error **errp);
+#endif
 
 struct QIGVMHandler {
     uint32_t type;
@@ -130,6 +137,10 @@ static struct QIGVMHandler handlers[] = {
       qigvm_initialization_guest_policy },
     { IGVM_VHT_MADT, IGVM_HEADER_SECTION_DIRECTIVE,
       qigvm_directive_madt },
+#ifdef CONFIG_FDT
+    { IGVM_VHT_DEVICE_TREE, IGVM_HEADER_SECTION_DIRECTIVE,
+      qigvm_directive_device_tree },
+#endif
 };
 
 static int qigvm_handler(QIgvm *ctx, uint32_t type, Error **errp)
@@ -790,6 +801,49 @@ static int qigvm_directive_snp_id_block(QIgvm *ctx, const uint8_t *header_data,
     return 0;
 }
 
+#ifdef CONFIG_FDT
+static int qigvm_directive_device_tree(QIgvm *ctx, const uint8_t *header_data,
+                                       Error **errp)
+{
+    const IGVM_VHS_PARAMETER *param = (const IGVM_VHS_PARAMETER *)header_data;
+    g_autofree void *fdt_packed = NULL;
+    QIgvmParameterData *param_entry;
+    uint32_t fdt_size;
+
+    param_entry = qigvm_find_param_entry(ctx, param->parameter_area_index);
+    if (param_entry == NULL) {
+        error_setg(errp, "IGVM: parameter area index %u not found",
+                   param->parameter_area_index);
+        return -1;
+    }
+
+    if (ctx->machine_state->fdt == NULL) {
+        error_setg(errp, "IGVM: device tree not available");
+        return -1;
+    }
+
+    fdt_size = fdt_totalsize(ctx->machine_state->fdt);
+    fdt_packed = g_memdup2(ctx->machine_state->fdt, fdt_size);
+
+    if (fdt_pack(fdt_packed)) {
+        error_setg(errp, "IGVM: failed to pack device tree");
+        return -1;
+    }
+
+    fdt_size = fdt_totalsize(fdt_packed);
+    if (fdt_size > param_entry->size) {
+        error_setg(errp,
+                   "IGVM: device tree size exceeds parameter area"
+                   " defined in IGVM file");
+        return -1;
+    }
+
+    memcpy(param_entry->data, fdt_packed, fdt_size);
+
+    return 0;
+}
+#endif
+
 static int qigvm_initialization_guest_policy(QIgvm *ctx,
                                        const uint8_t *header_data, Error **errp)
 {

hw/core/machine.c

@@ -1218,6 +1218,7 @@ static void machine_initfn(Object *obj)
     ms->kernel_cmdline = g_strdup("");
     ms->ram_size = mc->default_ram_size;
     ms->maxram_size = mc->default_ram_size;
+    ms->device_plane = 0;
 
     if (mc->nvdimm_supported) {
         ms->nvdimms_state = g_new0(NVDIMMState, 1);
@@ -1253,6 +1254,12 @@ static void machine_initfn(Object *obj)
                                    "ACPI Serial Port Console Redirection "
                                    "Table (spcr)");
 
+    /* Default Device Plane */
+    object_property_add_uint8_ptr(obj, "device-plane", &ms->device_plane,
+                                  OBJ_PROP_FLAG_READWRITE);
+    object_property_set_description(obj, "device-plane",
+                                    "Default plane to receive device IRQs");
+
     /* default to mc->default_cpus */
     ms->smp.cpus = mc->default_cpus;
     ms->smp.max_cpus = mc->default_cpus;
@@ -1761,6 +1768,15 @@ void qdev_machine_creation_done(void)
     register_global_state();
 }
 
+uint8_t qdev_default_plane(void)
+{
+    if (current_machine != NULL) {
+        return current_machine->device_plane;
+    } else {
+        return 0;
+    }
+}
+
 static const TypeInfo machine_info = {
     .name = TYPE_MACHINE,
     .parent = TYPE_OBJECT,

hw/core/qdev.c

@@ -662,6 +662,28 @@ static bool device_get_hotplugged(Object *obj, Error **errp)
     return dev->hotplugged;
 }
 
+static void device_get_plane(Object *obj, Visitor *v, const char *name,
+                             void *opaque, Error **errp)
+{
+    DeviceState *dev = DEVICE(obj);
+    uint8_t value = dev->plane;
+
+    visit_type_uint8(v, name, &value, errp);
+}
+
+static void device_set_plane(Object *obj, Visitor *v, const char *name,
+                             void *opaque, Error **errp)
+{
+    DeviceState *dev = DEVICE(obj);
+    uint8_t value;
+
+    if (!visit_type_uint8(v, name, &value, errp)) {
+        return;
+    }
+
+    dev->plane = value;
+}
+
 static void device_initfn(Object *obj)
 {
     DeviceState *dev = DEVICE(obj);
@@ -674,6 +696,7 @@ static void device_initfn(Object *obj)
     dev->instance_id_alias = -1;
     dev->realized = false;
     dev->allow_unplug_during_migration = false;
+    dev->plane = qdev_default_plane();
 
     QLIST_INIT(&dev->gpios);
     QLIST_INIT(&dev->clocks);
@@ -796,6 +819,9 @@ static void device_class_init(ObjectClass *class, const void *data)
                                    device_get_hotplugged, NULL);
     object_class_property_add_link(class, "parent_bus", TYPE_BUS,
                                    offsetof(DeviceState, parent_bus), NULL, 0);
+    object_class_property_add(class, "plane", "uint8",
+                              device_get_plane, device_set_plane,
+                              NULL, NULL);
 }
 
 static void do_legacy_reset(Object *obj, ResetType type)

hw/i386/Kconfig

@@ -17,6 +17,8 @@ config TDX
 
 config PC
     bool
+    select DEVICE_TREE
+    depends on FDT
     imply APPLESMC
     imply HYPERV
     imply ISA_IPMI_KCS

hw/i386/meson.build

@@ -28,6 +28,7 @@ i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'),
 i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c'))
 i386_ss.add(when: 'CONFIG_PC', if_true: files(
   'x86-common.c',
+  'x86_dt_common.c',
   'pc.c',
   'pc_sysfw.c',
   'acpi-build.c',

hw/i386/microvm-dt.c

@@ -73,6 +73,8 @@ static void dt_add_virtio(MicrovmMachineState *mms, VirtIOMMIOProxy *mmio)
         return;
     }
 
+    VirtIODevice *vdev = virtio_bus_get_device(mmio_virtio_bus);
+    uint8_t plane = object_property_get_int(OBJECT(vdev), "plane", &error_fatal);
     hwaddr base = dev->mmio[0].addr;
     hwaddr size = 512;
     unsigned index = (base - VIRTIO_MMIO_BASE) / size;
@@ -83,13 +85,15 @@ static void dt_add_virtio(MicrovmMachineState *mms, VirtIOMMIOProxy *mmio)
     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "virtio,mmio");
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "plane", plane);
     dt_add_microvm_irq(mms, nodename, irq);
     g_free(nodename);
 }
 
-static void dt_add_xhci(MicrovmMachineState *mms)
+static void dt_add_xhci(MicrovmMachineState *mms, DeviceState *dev)
 {
     const char compat[] = "generic-xhci";
+    uint8_t plane = object_property_get_int(OBJECT(dev), "plane", &error_fatal);
     MachineState *ms = MACHINE(mms);
     uint32_t irq = MICROVM_XHCI_IRQ;
     hwaddr base = MICROVM_XHCI_BASE;
@@ -101,12 +105,14 @@ static void dt_add_xhci(MicrovmMachineState *mms)
     qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "plane", plane);
     dt_add_microvm_irq(mms, nodename, irq);
     g_free(nodename);
 }
 
-static void dt_add_pcie(MicrovmMachineState *mms)
+static void dt_add_pcie(MicrovmMachineState *mms, DeviceState *dev)
 {
+    uint8_t plane = object_property_get_int(OBJECT(dev), "plane", &error_fatal);
     MachineState *ms = MACHINE(mms);
     hwaddr base = PCIE_MMIO_BASE;
     int nr_pcie_buses;
@@ -121,6 +127,7 @@ static void dt_add_pcie(MicrovmMachineState *mms)
     qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
     qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "plane", plane);
 
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
                                  2, PCIE_ECAM_BASE, 2, PCIE_ECAM_SIZE);
@@ -154,6 +161,7 @@ static void dt_add_pcie(MicrovmMachineState *mms)
 
 static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev)
 {
+    uint8_t plane = object_property_get_int(OBJECT(dev), "plane", &error_fatal);
     MachineState *ms = MACHINE(mms);
     hwaddr base = dev->mmio[0].addr;
     char *nodename;
@@ -181,6 +189,7 @@ static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev)
     qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
                                  2, base, 2, 0x1000);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "plane", plane);
 
     ph = qemu_fdt_alloc_phandle(ms->fdt);
     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", ph);
@@ -195,6 +204,7 @@ static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev)
     const char compat[] = "ns16550";
     uint32_t irq = object_property_get_int(OBJECT(dev), "irq", &error_fatal);
     hwaddr base = object_property_get_int(OBJECT(dev), "iobase", &error_fatal);
+    uint8_t plane = object_property_get_int(OBJECT(dev), "plane", &error_fatal);
     MachineState *ms = MACHINE(mms);
     hwaddr size = 8;
     char *nodename;
@@ -203,6 +213,7 @@ static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev)
     qemu_fdt_add_subnode(ms->fdt, nodename);
     qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "plane", plane);
     dt_add_microvm_irq(mms, nodename, irq);
 
     if (base == 0x3f8 /* com1 */) {
@@ -217,6 +228,7 @@ static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev)
     const char compat[] = "motorola,mc146818";
     uint32_t irq = object_property_get_uint(OBJECT(dev), "irq", &error_fatal);
     hwaddr base = object_property_get_uint(OBJECT(dev), "iobase", &error_fatal);
+    uint8_t plane = object_property_get_int(OBJECT(dev), "plane", &error_fatal);
     MachineState *ms = MACHINE(mms);
     hwaddr size = 8;
     char *nodename;
@@ -225,6 +237,7 @@ static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev)
     qemu_fdt_add_subnode(ms->fdt, nodename);
     qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "plane", plane);
     dt_add_microvm_irq(mms, nodename, irq);
     g_free(nodename);
 }
@@ -291,14 +304,14 @@ static void dt_setup_sys_bus(MicrovmMachineState *mms)
         /* xhci */
         obj = object_dynamic_cast(OBJECT(dev), TYPE_XHCI_SYSBUS);
         if (obj) {
-            dt_add_xhci(mms);
+            dt_add_xhci(mms, DEVICE(obj));
             continue;
         }
 
         /* pcie */
         obj = object_dynamic_cast(OBJECT(dev), TYPE_GPEX_HOST);
         if (obj) {
-            dt_add_pcie(mms);
+            dt_add_pcie(mms, DEVICE(obj));
             continue;
         }
 

hw/i386/pc.c

@@ -67,6 +67,7 @@
 #include "trace.h"
 #include "sev.h"
 #include CONFIG_DEVICES
+#include "x86_dt_common.h"
 
 #ifdef CONFIG_XEN_EMU
 #include "hw/xen/xen-legacy-backend.h"
@@ -522,6 +523,7 @@ void pc_machine_done(Notifier *notifier, void *data)
     PCMachineState *pcms = container_of(notifier,
                                         PCMachineState, machine_done);
     X86MachineState *x86ms = X86_MACHINE(pcms);
+    MachineState *machine = MACHINE(pcms);
 
     cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state,
                               &error_fatal);
@@ -546,6 +548,9 @@ void pc_machine_done(Notifier *notifier, void *data)
     }
 
     pc_cmos_init_late(pcms);
+    if (x86ms->igvm) {
+        dt_setup_x86(machine);
+    }
 }
 
 /* setup pci memory address space mapping into system address space */