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Merged
matth2k merged 1 commit into from
Feb 28, 2026
Merged

New implementation of FDCE and FDPE registers. #214

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6 changes: 4 additions & 2 deletions src/cost.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,9 @@ impl CostFunction<LutLang> for KLUTCostFn {
}
LutLang::Program(_) => 0,
LutLang::Bus(_) => 0,
LutLang::Fdre(_) | LutLang::Fdse(_) => self.reg_cost,
LutLang::Fdre(_) | LutLang::Fdse(_) | LutLang::Fdpe(_) | LutLang::Fdce(_) => {
self.reg_cost
}
LutLang::Cycle(_) => 0,
LutLang::Arg(_) => 0,
LutLang::Const(_) => 0,
Expand Down Expand Up @@ -193,7 +195,7 @@ impl CostFunction<LutLang> for GateCostFn {
}
LutLang::Program(_) => 0,
LutLang::Bus(_) => 0,
LutLang::Fdre(_) | LutLang::Fdse(_) => 1,
LutLang::Fdre(_) | LutLang::Fdse(_) | LutLang::Fdpe(_) | LutLang::Fdce(_) => 1,
LutLang::Cycle(_) => 0,
LutLang::Arg(_) => 0,
LutLang::Const(_) => 0,
Expand Down
2 changes: 1 addition & 1 deletion src/driver.rs
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Expand Up @@ -411,7 +411,7 @@ impl RewriteStrat {
}

/// The list of gates that must be reachable by the disassembling rewrite rule system.
pub const GATE_WHITELIST_STR: &str = "MUX,AND,OR,XOR,NOT,INV,FDRE,FDSE,NAND,NOR";
pub const GATE_WHITELIST_STR: &str = "MUX,AND,OR,XOR,NOT,INV,FDRE,FDSE,FDPE,FDCE,NAND,NOR";

impl OptStrat {
/// Create an extraction strategy from a comma-separated list of gates.
Expand Down
13 changes: 11 additions & 2 deletions src/lut.rs
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Expand Up @@ -35,6 +35,8 @@ define_language! {
"BUS" = Bus(Box<[Id]>), // a bus of nodes
"REG" = Fdre([Id; 4]), // D, C, CE, R
"FDSE" = Fdse([Id; 4]), // D, C, CE, S
"FDPE" = Fdpe([Id; 4]), // D, C, CE, PR
"FDCE" = Fdce([Id; 4]), // D, C, CE, CLR
"ARG" = Arg([Id; 1]),
"CYCLE" = Cycle([Id; 1]),
}
Expand Down Expand Up @@ -296,7 +298,7 @@ impl LutLang {
}
Ok(bv)
}
LutLang::Fdre(_) | LutLang::Fdse(_) => {
LutLang::Fdre(_) | LutLang::Fdse(_) | LutLang::Fdpe(_) | LutLang::Fdce(_) => {
Err("REG is not combinational logic".to_string())
}
LutLang::Arg(_) => Err("ARG is not combinational logic".to_string()),
Expand Down Expand Up @@ -330,6 +332,8 @@ impl LutLang {
| (LutLang::Bus(_), LutLang::Bus(_))
| (LutLang::Fdre(_), LutLang::Fdre(_))
| (LutLang::Fdse(_), LutLang::Fdse(_))
| (LutLang::Fdpe(_), LutLang::Fdpe(_))
| (LutLang::Fdce(_), LutLang::Fdce(_))
| (LutLang::Arg(_), LutLang::Arg(_))
| (LutLang::Cycle(_), LutLang::Cycle(_)) => {
for (a, b) in self.children().iter().zip(other.children()) {
Expand Down Expand Up @@ -778,7 +782,12 @@ impl<'a> LutExprInfo<'a> {
let cse = self.get_cse();
cse.as_ref()
.iter()
.filter(|n| matches!(n, LutLang::Fdre(_) | LutLang::Fdse(_)))
.filter(|n| {
matches!(
n,
LutLang::Fdre(_) | LutLang::Fdse(_) | LutLang::Fdpe(_) | LutLang::Fdce(_)
)
})
.count() as u64
}

Expand Down
4 changes: 4 additions & 0 deletions src/netlist.rs
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Expand Up @@ -478,7 +478,9 @@ impl LogicFunc<LutLang> for PrimitiveCell {
PrimitiveType::MUX => Some(LutLang::Mux(children.try_into().ok()?)),
PrimitiveType::NOT => Some(LutLang::Not(children.try_into().ok()?)),
PrimitiveType::FDRE => Some(LutLang::Fdre(children.try_into().ok()?)),
PrimitiveType::FDPE => Some(LutLang::Fdpe(children.try_into().ok()?)),
PrimitiveType::FDSE => Some(LutLang::Fdse(children.try_into().ok()?)),
PrimitiveType::FDCE => Some(LutLang::Fdce(children.try_into().ok()?)),
_ if self.ptype.is_lut() => Some(LutLang::Lut(children.into())),
_ => None,
}
Expand Down Expand Up @@ -610,6 +612,8 @@ impl LogicCell<PrimitiveCell> for LutLang {
LutLang::DC => PrimitiveCell::from_constant(Logic::X)?,
LutLang::Fdre(_) => PrimitiveCell::new(PrimitiveType::FDRE, None),
LutLang::Fdse(_) => PrimitiveCell::new(PrimitiveType::FDSE, None),
LutLang::Fdpe(_) => PrimitiveCell::new(PrimitiveType::FDPE, None),
LutLang::Fdce(_) => PrimitiveCell::new(PrimitiveType::FDCE, None),
LutLang::Xor(_) => PrimitiveCell::new(PrimitiveType::XOR, None),
LutLang::Lut(l) => match l.len() {
2 => PrimitiveCell::new(PrimitiveType::LUT1, None),
Expand Down
50 changes: 43 additions & 7 deletions src/verilog.rs
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Expand Up @@ -246,6 +246,8 @@ pub enum PrimitiveType {
GND,
FDRE,
FDSE,
FDPE,
FDCE,
MAJ3,
}

Expand Down Expand Up @@ -273,7 +275,7 @@ impl PrimitiveType {
Self::LUT5 => 5,
Self::LUT6 => 6,
Self::VCC | Self::GND => 0,
Self::FDRE | Self::FDSE => 4,
Self::FDRE | Self::FDSE | Self::FDPE | Self::FDCE => 4,
Self::MAJ3 => 3,
}
}
Expand Down Expand Up @@ -380,6 +382,18 @@ impl PrimitiveType {
"CE".to_string(),
"S".to_string(),
],
Self::FDPE => vec![
"D".to_string(),
"C".to_string(),
"CE".to_string(),
"PRE".to_string(),
],
Self::FDCE => vec![
"D".to_string(),
"C".to_string(),
"CE".to_string(),
"CLR".to_string(),
],
}
}

Expand All @@ -405,7 +419,7 @@ impl PrimitiveType {
| Self::MUXF9 => "O".to_string(),
Self::VCC => "P".to_string(),
Self::GND => "G".to_string(),
Self::FDRE | Self::FDSE => "Q".to_string(),
Self::FDRE | Self::FDSE | Self::FDPE | Self::FDCE => "Q".to_string(),
Self::MUX2 | Self::XOR2 => "Z".to_string(),
_ => "ZN".to_string(),
}
Expand All @@ -421,12 +435,16 @@ impl PrimitiveType {

/// Returns true if the primitive is not a LUT
pub fn is_gate(&self) -> bool {
!self.is_lut() && !matches!(self, Self::VCC | Self::GND | Self::FDRE | Self::FDSE)
!self.is_lut()
&& !matches!(
self,
Self::VCC | Self::GND | Self::FDRE | Self::FDSE | Self::FDPE | Self::FDCE
)
}

/// Returns true if the primitive is a register (FDRE,FDSE)
/// Returns true if the primitive is a register (FDRE,FDSE,FDPE, FDCE)
pub fn is_reg(&self) -> bool {
matches!(self, Self::FDRE | Self::FDSE)
matches!(self, Self::FDRE | Self::FDSE | Self::FDPE | Self::FDCE)
}

/// Get the area of a minimum sized primitive of [PrimitiveType]
Expand Down Expand Up @@ -521,6 +539,8 @@ impl FromStr for PrimitiveType {
"GND" => Ok(Self::GND),
"FDRE" => Ok(Self::FDRE),
"FDSE" => Ok(Self::FDSE),
"FDPE" => Ok(Self::FDPE),
"FDCE" => Ok(Self::FDCE),
"MAJ3" => Ok(Self::MAJ3),
_ => Err(format!("Unknown primitive type {pre}")),
}
Expand Down Expand Up @@ -617,7 +637,10 @@ impl SVPrimitive {
prim.set_attribute("VAL".to_string(), "1'b0".to_string());
return prim;
}
PrimitiveType::FDRE | PrimitiveType::FDSE => {
PrimitiveType::FDRE
| PrimitiveType::FDSE
| PrimitiveType::FDPE
| PrimitiveType::FDCE => {
prim.set_attribute("INIT".to_string(), "1'hx".to_string());
}
_ => {}
Expand Down Expand Up @@ -664,7 +687,10 @@ impl SVPrimitive {
prim.set_attribute("VAL".to_string(), "1'b0".to_string());
return prim;
}
PrimitiveType::FDRE | PrimitiveType::FDSE => {
PrimitiveType::FDRE
| PrimitiveType::FDSE
| PrimitiveType::FDPE
| PrimitiveType::FDCE => {
prim.set_attribute("INIT".to_string(), "1'hx".to_string());
}
_ => {}
Expand Down Expand Up @@ -927,6 +953,8 @@ impl VerilogEmission for LutLang {
LutLang::Xor(_) => Some(PrimitiveType::XOR),
LutLang::Fdre(_) => Some(PrimitiveType::FDRE),
LutLang::Fdse(_) => Some(PrimitiveType::FDSE),
LutLang::Fdpe(_) => Some(PrimitiveType::FDPE),
LutLang::Fdce(_) => Some(PrimitiveType::FDCE),
_ => None,
}
}
Expand Down Expand Up @@ -963,6 +991,8 @@ impl VerilogEmission for LutLang {
| LutLang::Not(_)
| LutLang::Fdre(_)
| LutLang::Fdse(_)
| LutLang::Fdpe(_)
| LutLang::Fdce(_)
| LutLang::Xor(_) => {
let inputs = self.children();
let gate_type = self
Expand Down Expand Up @@ -1164,6 +1194,12 @@ impl VerilogParsing for LutLang {
PrimitiveType::FDSE => {
Ok(expr.add(LutLang::Fdse([ids[0], ids[1], ids[2], ids[3]])))
}
PrimitiveType::FDPE => {
Ok(expr.add(LutLang::Fdpe([ids[0], ids[1], ids[2], ids[3]])))
}
PrimitiveType::FDCE => {
Ok(expr.add(LutLang::Fdce([ids[0], ids[1], ids[2], ids[3]])))
}
PrimitiveType::LUT1
| PrimitiveType::LUT2
| PrimitiveType::LUT3
Expand Down