Add CachePadded variants with capped max alignment#1118
Add CachePadded variants with capped max alignment#1118Jules-Bertholet wants to merge 3 commits intocrossbeam-rs:masterfrom
CachePadded variants with capped max alignment#1118Conversation
These are useful for ensuring that values don't *cross* a cache line, without restricting whether they can *share* one.
Given how we set our aarch64 and x86_64's alignments, I don't think this implementation is sufficient. I'm also interested in what concrete cases this would be useful. |
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My phrasing of "don't cross a cache line" was suboptimal; I've changed it to "cross as few cache lines as possible", which is what I really want. My use case is that I have a large, but not too large, value (a lookup table), and I want it to take up as few cache lines as possible. |
Could you elaborate? |
On some CPUs, cache line is 64-byte, and on some, it is 128-byte. We choice 128-byte to avoid false sharing in either case, but if you wish to use it for a purpose other than avoiding false sharing, the opposite choice may be necessary. (By the way, on AArch64, there is CPU with 256-byte cache line (A64FX), but we ignore it at this time since it is very rare.) |
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These are useful for ensuring that values cross as few cache lines as possible, without restricting whether they can share one.