[Monitor + Interp] Wishbone subordinate example

monitor/tests/wishbone/wishbone.out

@@ -0,0 +1,18 @@
+// trace 0
+trace {
+    read(0, 0);
+    write(0, 0);
+    read(0, 3);
+    read(0, 5);
+    read(0, 7);
+    read(0, 9);
+    read(0, 11);
+    read(0, 0);
+    write(0, 0);
+    read(0, 3);
+    read(0, 5);
+    read(0, 7);
+    read(0, 9);
+    read(0, 11);
+    read(0, 0);
+}

monitor/tests/wishbone/wishbone.prot

@@ -0,0 +1,113 @@
+// ARGS: --wave wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk
+
+// Wishbone B4 (Pipeline mode) subordinate
+struct WBSubordinate {
+    // Cycle is high anytime an active pipeline session is occurring
+    in i_cyc: u1,
+
+    // Strobe is high when there is a request to the subordinate
+    // (akin to Valid in AXI-Lite, i.e. they indicate the manager
+    // has something to transfer)
+    in i_stb: u1,
+
+    // Write-enable (true for write-requests)
+    in i_we: u1,
+
+    // Address of the request
+    in i_addr: u1,
+
+    // Data to be written
+    in i_data: u32,
+
+    // Response from the subordinate, indicating that the request
+    // has been fulfilled.
+    out o_ack: u1,
+
+    // True on any cycle when the subordinate can't accept requests
+    // False when a request can be accepted
+    // (i.e. the opposite of Ready in AXI-Lite)
+    out o_stall: u1,
+
+    // Data returned by the subordinate to the manager
+    // This is valid only when ACK is true
+    out o_data: u32,
+}
+
+// Both cyc & stb are low when the subordinate is low,
+// everything else is DontCare
+#[idle]
+prot idle<DUT: WBSubordinate>() {
+    DUT.i_cyc  := 1'b0;
+    DUT.i_stb  := 1'b0;
+    DUT.i_we   := X;
+    DUT.i_addr := X;
+    DUT.i_data := X;
+    step();
+}
+
+// Writes a `data` value to the subordinate.
+// Wishbone says to hold all request signals while stalled (stall=1),
+// i.e. when the subordinate is busy processing a previous request.
+prot write<DUT: WBSubordinate>(in addr: u1, in data: u32) {
+    DUT.i_cyc  := 1'b1;
+    DUT.i_stb  := 1'b1;
+    DUT.i_we   := 1'b1;
+    DUT.i_addr := addr;
+    DUT.i_data := data;
+
+    // Wait till the subordinate Acks
+    // Note that in the Verilog, after the subordinate acks, 
+    // `o_stall` is assigned combinationally (`o_stall = busy && i_we`), 
+    // so we don't need another while-loop to wait for `stall` to become 0
+    while (DUT.o_ack == 1'b0) {
+        step();
+    }
+
+    // Data is updated combinationally in the same cycle as the ack,
+    // so no separate cycle for data transfer is needed
+    assert_eq(DUT.o_data, data);
+
+    // Set other inputs to DontCare
+    // Note that the waveform produced by their C++ test-bench keeps 
+    // `cyc` and `stb` high, so we don't set `cyc` and `stb` to 0 here
+    DUT.i_cyc := X;
+    DUT.i_stb := X;
+    DUT.i_we := X;
+    DUT.i_addr := X;
+    DUT.i_data := X;
+
+    step();
+}
+
+// Reads a value from the subordinate
+// (the `data` is conveyed via output parameters)
+prot read<DUT: WBSubordinate>(in addr: u1, out data: u32) {
+    DUT.i_cyc  := 1'b1;
+    DUT.i_stb  := 1'b1;
+    DUT.i_we   := 1'b0;
+    DUT.i_addr := addr;
+    DUT.i_data := X;
+
+    // Wait for subordinate to Ack
+    // (When we're reading, the write-enable is always 0, 
+    // but in the Verilog, `stall` is a boolean AND of `i_we` and another
+    // signal, so `stall` is always 0 when we're reading, so we don't 
+    // need another while-loop to wait for `stall` to become 0)
+    while (DUT.o_ack == 1'b0) {
+        step();
+    }
+
+    // Data is updated combinationally in the same cycle as the ack,
+    // so no separate cycle for data transfer is needed
+    assert_eq(DUT.o_data, data);
+
+    // Set other inputs to DontCare
+    // Note that the waveform produced by their C++ test-bench keeps 
+    // `cyc` and `stb` high, so we don't set `cyc` and `stb` to 0 here
+    DUT.i_cyc := X;
+    DUT.i_stb := X;
+    DUT.i_we := X;
+    DUT.i_addr := X;
+
+    step();
+}

protocols/tests/wishbone/.gitignore

@@ -0,0 +1,3 @@
+obj_dir/*
+reqwalker_tb
+*.vcd

protocols/tests/wishbone/Makefile

@@ -0,0 +1,53 @@
+################################################################################
+##
+## Filename: 	Makefile
+##
+## Project:	Verilog Tutorial Example file
+##
+## Purpose:	Builds the Verilator request-walker bus slave example
+##
+## Targets:
+##
+##	The (default) or all target will build a verilator simulation for the
+##	Request Walker.
+##
+##	clean	Removes all build products
+##
+## Creator:	Dan Gisselquist, Ph.D.
+##		Gisselquist Technology, LLC
+##
+################################################################################
+##
+## Written and distributed by Gisselquist Technology, LLC
+##
+## This program is hereby granted to the public domain.
+##
+## This program is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.
+##
+################################################################################
+##
+##
+.PHONY: all
+all: reqwalker_tb
+
+VERILATOR=verilator
+VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
+VINC := $(VERILATOR_ROOT)/include
+
+obj_dir/Vreqwalker.cpp: reqwalker.v
+	$(VERILATOR) --trace -Wall -cc reqwalker.v
+
+obj_dir/Vreqwalker__ALL.a: obj_dir/Vreqwalker.cpp
+	make --no-print-directory -C obj_dir -f Vreqwalker.mk
+
+reqwalker_tb: reqwalker.cpp obj_dir/Vreqwalker__ALL.a
+	g++ -I$(VINC) -I obj_dir $(VINC)/verilated.cpp	\
+		$(VINC)/verilated_vcd_c.cpp			\
+		$(VINC)/verilated_threads.cpp reqwalker.cpp	\
+		obj_dir/Vreqwalker__ALL.a -o reqwalker_tb
+
+.PHONY: clean
+clean:
+	rm -rf obj_dir/ reqwalker_tb reqwalker.vcd reqwalker_cvr/ reqwalker_prf/

protocols/tests/wishbone/reqwalker.cpp

@@ -0,0 +1,149 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: 	redqalker.cpp
+//
+// Project:	Verilog Tutorial Example file
+//
+// Purpose:	This is an example Verilator test bench driver file reqwalker
+//		module.
+//
+// Creator:	Dan Gisselquist, Ph.D.
+//		Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Written and distributed by Gisselquist Technology, LLC
+//
+// This program is hereby granted to the public domain.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+#include <stdio.h>
+#include <stdlib.h>
+#include "Vreqwalker.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+// Required by Verilator when not using SystemC
+double sc_time_stamp() { return 0; }
+
+int	tickcount = 0;
+Vreqwalker	*tb;
+VerilatedVcdC	*tfp;
+
+void	tick(void) {
+	tickcount++;
+
+	tb->eval();
+	if (tfp)
+		tfp->dump(tickcount * 10 - 2);
+	tb->i_clk = 1;
+	tb->eval();
+	if (tfp)
+		tfp->dump(tickcount * 10);
+	tb->i_clk = 0;
+	tb->eval();
+	if (tfp) {
+		tfp->dump(tickcount * 10 + 5);
+		tfp->flush();
+	}
+}
+
+unsigned wb_read(unsigned a) {
+	tb->i_cyc = tb->i_stb = 1;
+	tb->i_we  = 0;
+	tb->eval(); // update o_stall, which depends combinationally on i_we
+	tb->i_addr= a;
+	// Make the request
+	while(tb->o_stall)
+		tick();
+	tick();
+	tb->i_stb = 0;
+	// Wait for the ACK
+	while(!tb->o_ack)
+		tick();
+	// Idle the bus, and read the response
+	tb->i_cyc = 0;
+	return tb->o_data;
+}
+
+void wb_write(unsigned a, unsigned v) {
+	tb->i_cyc = tb->i_stb = 1;
+	tb->i_we  = 1;
+	tb->eval(); // update o_stall, which depends combinationally on i_we
+	tb->i_addr= a;
+	tb->i_data= v;
+	// Make the bus request
+	while(tb->o_stall)
+		tick();
+	tick();
+	tb->i_stb = 0;
+	// Wait for the acknowledgement
+	while(!tb->o_ack)
+		tick();
+	// Idle the bus and return
+	tb->i_cyc = tb->i_stb = 0;
+}
+
+int main(int argc, char **argv) {
+	int	last_led, last_state = 0, state = 0;
+
+	// Call commandArgs first!
+	Verilated::commandArgs(argc, argv);
+
+	// Instantiate our design
+	tb = new Vreqwalker;
+
+	// Generate a trace
+	Verilated::traceEverOn(true);
+	tfp = new VerilatedVcdC;
+	tb->trace(tfp, 99);
+	tfp->open("reqwalker.vcd");
+
+	last_led = tb->o_led;
+
+	// Read from the current state
+	printf("Initial state is: 0x%02x\n",
+		wb_read(0));
+
+	for(int cycle=0; cycle<2; cycle++) {
+		// Wait five clocks
+		for(int i=0; i<5; i++)
+			tick();
+
+		// Start the LEDs cycling
+		wb_write(0,0);
+		tick();
+
+		while((state = wb_read(0))!=0) {
+			if ((state != last_state)
+				||(tb->o_led != last_led)) {
+				printf("%6d: State #%2d ",
+					tickcount, state);
+				for(int j=0; j<6; j++) {
+					if(tb->o_led & (1<<j))
+						printf("O");
+					else
+						printf("-");
+				} printf("\n");
+			}
+
+			last_state = state;
+			last_led = tb->o_led;
+
+			// Idle cycle between reads so the VCD captures i_stb=0,
+			// making each transaction visible as a separate event to the monitor
+			tb->i_cyc = tb->i_stb = 0;
+			tick();
+		}
+	}
+
+	tfp->close();
+	delete tfp;
+	delete tb;
+}

protocols/tests/wishbone/reqwalker.sby

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+[tasks]
+cvr
+prf
+
+[options]
+cvr: mode cover
+prf: mode prove
+
+[engines]
+smtbmc
+
+[script]
+read -formal reqwalker.v
+prep -top reqwalker
+
+[files]
+reqwalker.v