Added avionics PCB :)))

[Babyyoda777]

No description provided.

[AaronDanton]

Only a few minor comments to be fixed

• Can you run the ERC. This brings up errors about the unused pins on the main chip, it might be worth replacing the labels with unused pin crosses
• Are you able to put one of the LoRa pins on to the back copper to remove the serpentine, specifically the LoRa pin 15 GPIO 17
• The DRC also has a few errors, most are from the USB C connector that can be ignored but there is a minor complaint about clearance around VRG_AVDD
• There is a warning about the BME text not being flipped which might be worth fixing

Other comments:

• Why 4 layers, and any reason for 2 grounds?

Do you mind also putting the CUSF Logo onto the board and feel free to put your name in the silkscreen. The logo is in the drive (logo-black.svg)

[Babyyoda777]

Only a few minor comments to be fixed

• Can you run the ERC. This brings up errors about the unused pins on the main chip, it might be worth replacing the labels with unused pin crosses
• Are you able to put one of the LoRa pins on to the back copper to remove the serpentine, specifically the LoRa pin 15 GPIO 17
• The DRC also has a few errors, most are from the USB C connector that can be ignored but there is a minor complaint about clearance around VRG_AVDD
• There is a warning about the BME text not being flipped which might be worth fixing

Other comments:

• Why 4 layers, and any reason for 2 grounds?

Do you mind also putting the CUSF Logo onto the board and feel free to put your name in the silkscreen. The logo is in the drive (logo-black.svg)

Hi, thanks for the review! Will fix the ERC errors soon, I had originally left all the GPIO pins labelled incase we needed to add/remove anything to them. Fixed the serpentine trace as well.

USB-C errors can be ignored, the footprint is well within JLCPCB manufacturing limits. Will fix the text soon too and add the logos!

As for the 4 layers, it's needed for the 50ohm impedance matching required by the LoRa antenna input traces (although it is quite short). 4 layers is also not too much more expensive (maybe $5) and is nice to have.

[AKCircuit]

Seems like a very compact and well laid out design. Just a few minor points:

NB: references to coordinates are in the format (X mm, Y mm)

• Running the DRC, it seems the +1.1V via at (149.68, 98.58) is not connected to anything - is this meant to be connected in parallel to the adjacent +1.1V via?
• GPIO15 seems to be connected to a via at (146.87, 109.94), but this does not then connect to anything else? The schematic appears to suggest GPIO15 needn't be connected to anything - is this connection just included so that the pin can be more easily probed for debugging?
• The routed slot around the BMP388 (U6) appears quite close to the edge of the PCB (approx. 0.5 mm), which doesn't appear to leave much margin for error. The narrow strip of PCB between the slot and the edge of the board might be quite vulnerable to breaking, especially given the +/- 0.1 mm dimensional tolerance JLC quote for CNC routing. Also, would you mind just double checking that the width of this ~300 degree arc-shaped slot is within the manufacturing capabilities? JLC give a min width of 1 mm for non-plated slots, and this slot appears to be approx. 0.5 mm wide.

[Babyyoda777]

Seems like a very compact and well laid out design. Just a few minor points:

NB: references to coordinates are in the format (X mm, Y mm)

• Running the DRC, it seems the +1.1V via at (149.68, 98.58) is not connected to anything - is this meant to be connected in parallel to the adjacent +1.1V via?
• GPIO15 seems to be connected to a via at (146.87, 109.94), but this does not then connect to anything else? The schematic appears to suggest GPIO15 needn't be connected to anything - is this connection just included so that the pin can be more easily probed for debugging?
• The routed slot around the BMP388 (U6) appears quite close to the edge of the PCB (approx. 0.5 mm), which doesn't appear to leave much margin for error. The narrow strip of PCB between the slot and the edge of the board might be quite vulnerable to breaking, especially given the +/- 0.1 mm dimensional tolerance JLC quote for CNC routing. Also, would you mind just double checking that the width of this ~300 degree arc-shaped slot is within the manufacturing capabilities? JLC give a min width of 1 mm for non-plated slots, and this slot appears to be approx. 0.5 mm wide.

1. Yes that via is simply in parallel, I have connected them now.

2. GPIO15 was just broken out incase I needed to use it down the line for something but ended up not needed it. I have left it as is since it's not critical to anything.

3. Re did the positioning so its 1mm slot with now and positioned towards board edge.