Seeking Feedback on Static Analysis Results for This Project​

[QinlinChen]

Hi @samsoniuk

We are a research team working to improve hardware reliability through programming language techniques, and we hope to contribute to the open-source hardware community like you. Actually, the issue #99 was automatically detected by our tool within seconds. We would greatly appreciate about one minute of your time to provide brief feedback based on this issue.

Background: We are developing a Verilog static analysis tool. Unlike traditional linting tools that check code syntax and patterns, our tool is designed to uncover deeper semantic bugs without requiring simulation, such as missing resets for key registers (it can distinguish registers unnecessary to reset and not report them), gated clocks, the use of undefined variables, and unreachable states. It is not LLM-based and provides algorithmic guarantees. We ran our tool two months ago on your project and reported two of three findings we believe are most relevant in this issue.

We welcome your feedback: Do you find such a static analysis tool would be helpful for avoiding potential oversights or risks in the early-stage of hardware development? If so, to what extent would you be interested in using such a tool?

Thank you very much for your time. We are eager to learn about any needs for hardware static analysis to help us improve our tool. If there are specific hardware issues you would like to see automatically detected, please feel free to email us (qinlinchen@smail.nju.edu.cn). We are happy to develop additional analyses based on your needs. After adding more features, we plan to open source the project by the end of this year!