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dhruvmittal41/README.md

> whoami

Engineer    : Dhruv Mittal
Degree      : B.Tech Electrical Engineering  [Year 3]
Origin      : India  🇮🇳
Core        :
  ├─ Computer Architecture   → pipelines, memory hierarchy, ISA design
  ├─ Hardware Accelerators   → efficient HW for transformer attention
  ├─ RTL / Digital Design    → Verilog, SystemVerilog, synthesis
  └─ Systems Foundations     → digital logic, signals & systems
Interest    : Making attention mechanisms cheaper to compute in silicon
Stage       : Undergrad, coursework + independent projects in progress
Goal        : Research experience in VLSI / computer architecture labs

> cat /proc/skills

Hardware & RTL

Verilog SystemVerilog Vivado

Foundations

Core Digital Logic Comp Arch Signals

Toolchain

Tools


> ls -la ./interests

Area What I'm Exploring
🧮 Hardware Accelerators Architectures for accelerating transformer attention computation — the core focus of my current independent work
🏗️ Computer Architecture Pipelining, memory hierarchy, and ISA-level design tradeoffs from coursework and self-study
🔲 RTL / Digital Design Implementing and simulating digital logic in Verilog/SystemVerilog, synthesis flows in Vivado
Efficient AI Hardware Reading up on how ML workloads map to hardware — where the bottlenecks are and how custom datapaths help

📌 I'm currently building projects in this space — repos and writeups will be added here as they're completed, not before. No vaporware.


> ./build --profile

/* ════════════════════════════════════════════════════════════════
   ENGINEER PROFILE  ·  Rev 1.0  ·  @dhruvmittal41
   ════════════════════════════════════════════════════════════════ */
#include <stdio.h>
#include <stdint.h>

typedef enum { COMP_ARCH, ACCELERATORS, RTL_DESIGN, FOUNDATIONS } Domain_t;

typedef struct {
    const char *name;
    const char *degree;
    Domain_t    focus[4];
    const char *stack[5];
    const char *interest;
    const char *goal;
} Engineer_t;

static const Engineer_t dhruv = {
    .name     = "Dhruv Mittal",
    .degree   = "B.Tech EE  (Year 3)",
    .focus    = { COMP_ARCH, ACCELERATORS, RTL_DESIGN, FOUNDATIONS },
    .stack    = { "Verilog", "SystemVerilog", "Vivado", "C/C++", "Python" },
    .interest = "Efficient hardware for transformer attention",
    .goal     = "Research role in VLSI / computer architecture",
};

int main(void) {
    printf("[BOOT]  %s  ·  %s\n", dhruv.name, dhruv.degree);
    printf("[FOCUS] %s\n", dhruv.interest);
    printf("[NEXT]  %s\n", dhruv.goal);
    return 0;
}

> htop — live stats 〕




> ping --connect

GitHub Gmail LinkedIn


"Attention is expensive. Making it cheap in silicon is the fun part."

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  4. System_Verilog_Practice System_Verilog_Practice Public

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    This Repo contains many simple hardware design and digital design related mini and big projects that i build as i learn