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pre-commit: PR134403 #2239

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@dtcxzyw dtcxzyw commented Apr 4, 2025

Link: llvm/llvm-project#134403
Requested by: @dtcxzyw

@github-actions github-actions bot mentioned this pull request Apr 4, 2025
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dtcxzyw commented Apr 4, 2025

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runner: ariselab-64c-v2
baseline: llvm/llvm-project@5fbd065
patch: llvm/llvm-project#134403
sha256: a5bb33c390b493e15473848911d775a38f358e90dd3253fefb184c6b6a7b1b0c
commit: 6d21fe9

1139 files changed, 1330067 insertions(+), 1331039 deletions(-)

Improvements:
  memcpyopt.NumStackMove 58478 -> 58573 +0.16%
  correlated-value-propagation.NumDeadCases 68835 -> 68874 +0.06%
  correlated-value-propagation.NumAnd 29995 -> 30002 +0.02%
  sccp.NumDeadBlocks 627050 -> 627152 +0.02%
  correlated-value-propagation.NumNSW 548840 -> 548917 +0.01%
  correlated-value-propagation.NumNUW 513043 -> 513086 +0.01%
  correlated-value-propagation.NumNNeg 84546 -> 84552 +0.01%
  jump-threading.NumFolds 2221871 -> 2221982 +0.00%
  correlated-value-propagation.NumAddNSW 236444 -> 236454 +0.00%
  correlated-value-propagation.NumSelects 212100 -> 212107 +0.00%
Regressions:
  correlated-value-propagation.NumPhis 1115077 -> 1114861 -0.02%
  memcpyopt.NumCallSlot 589799 -> 589742 -0.01%
  simplifycfg.NumFoldValueComparisonIntoPredecessors 479355 -> 479313 -0.01%
  jump-threading.NumThreads 2374328 -> 2374191 -0.01%
  correlated-value-propagation.NumNonNull 8259640 -> 8259221 -0.01%
  simplifycfg.NumSinkCommonCode 308148 -> 308139 -0.00%
  simplifycfg.NumSinkCommonInstrs 654451 -> 654434 -0.00%
  licm.NumLoadPromoted 66104 -> 66103 -0.00%
  constraint-elimination.NumCondsRemoved 2898529 -> 2898497 -0.00%
  licm.NumPromotionCandidates 462206 -> 462201 -0.00%

1 1 bench/abseil-cpp/optimized/inlined_vector_test.ll
2 1 bench/actix-rs/optimized/4j8yieid8zrlsuh3.ll
4 7 bench/actix-rs/optimized/xcr5yeosl21p44j.ll
6 6 bench/clap-rs/optimized/5651dp9k16h53y8x.ll
7 7 bench/clap-rs/optimized/gk6w3l154s6ch7z.ll
7 13 bench/coreutils-rs/optimized/qcad8r5ga44hvbl.ll
6 12 bench/diesel-rs/optimized/1k9itxwmy6phzvjw.ll
24 48 bench/diesel-rs/optimized/1mpore8avqzhq9r4.ll
5 8 bench/diesel-rs/optimized/2nqojkvzec127ieh.ll
3 6 bench/diesel-rs/optimized/4l61q7h3mw8r4045.ll
84 83 bench/html5ever-rs/optimized/38n20yzo26sy51uu.ll
11 11 bench/image-rs/optimized/1clnprdgqfw2q9lq.ll
4 4 bench/image-rs/optimized/4srzh4wujeew249y.ll
25 25 bench/just-rs/optimized/23nlf67cmm9na4ci.ll
50 49 bench/linux/optimized/reboot.ll
13 13 bench/meilisearch-rs/optimized/4p6euf9p6jz4j36m.ll
17 20 bench/ockam-rs/optimized/23pvw3nj6m0p9wnd.ll
2 2 bench/opencv/optimized/sparse_match_interpolators.ll
19 19 bench/regex-rs/optimized/3ixfkxlmcuecmmus.ll
92 91 bench/rust-analyzer-rs/optimized/1siyoufv1amkefl9.ll
48 36 bench/rust-analyzer-rs/optimized/3j0nbdwupb3iwt86.ll
58 57 bench/rust-analyzer-rs/optimized/4mnb5su7whazh2aj.ll
9 9 bench/rustfmt-rs/optimized/1mznjg1e09hdetpr.ll
3 3 bench/rustfmt-rs/optimized/2iek5i6kf8wd1vt9.ll
102 102 bench/rustfmt-rs/optimized/2vbyym84o66crvo9.ll
33 33 bench/rustfmt-rs/optimized/3sx1t619hmuq0zz7.ll
1 1 bench/rustfmt-rs/optimized/5genfix4t5066ss.ll
66 66 bench/rustfmt-rs/optimized/s8gyre8ye3tvwam.ll
15 15 bench/rustfmt-rs/optimized/x2cb3fifm47d4t5.ll
24 24 bench/syn/optimized/19z3k5eqgbxjiezn.ll
22 22 bench/syn/optimized/1isw8n6q6q0tgdaq.ll
13 16 bench/syn/optimized/ofvfd67uyaewjlc.ll
74 73 bench/tokenizers-rs/optimized/10h1ju7dwsvagf79.ll
8 8 bench/tokenizers-rs/optimized/2d3ht47jz0iets91.ll
10 10 bench/tokenizers-rs/optimized/2mot01sr7ebui81b.ll
37 37 bench/tokenizers-rs/optimized/40hmx6rev8evi2bx.ll
14 14 bench/tokenizers-rs/optimized/58hth72z9dib25am.ll
5 5 bench/tokenizers-rs/optimized/5e69nv5s2wu1vtyr.ll
23 23 bench/tree-sitter-rs/optimized/23gl3z4j3ugr749z.ll
65 64 bench/tree-sitter-rs/optimized/4pzbn5o6oxp3emp4.ll
47 47 bench/turborepo-rs/optimized/eyin3u3cupdp2wcinr2t4x92g.ll
16 24 bench/typst-rs/optimized/1ru1rhojhbz2vfey.ll
44 55 bench/typst-rs/optimized/3dimj4rf5dyrieyi.ll
7 10 bench/typst-rs/optimized/4qskctz4kwc33g7b.ll
3 2 bench/wasmtime-rs/optimized/322yw2dra6hhv794.ll
6 4 bench/wasmtime-rs/optimized/3kgdlzjlx2p3jthq.ll
5 4 bench/wasmtime-rs/optimized/3w5lei6xclrfo3sz.ll
8 4 bench/wasmtime-rs/optimized/4nkh38vfk0kb3m00.ll
3 6 bench/wasmtime-rs/optimized/sa4imocsqq56n3l.ll
71 74 bench/zed-rs/optimized/6r72qkitrvbw1ftdc9j10udqo.ll
47 65 bench/zed-rs/optimized/7almbq0vtpgp7q0c9d6k1td97.ll
8 11 bench/zed-rs/optimized/9awmqr28bdho83r0fgrej0t00.ll
27 30 bench/zed-rs/optimized/9iau01omm5rr9yzc2t1pdns1t.ll
47 50 bench/zed-rs/optimized/b0jacrvunbgse6y69p1vx4gkq.ll
26 29 bench/zed-rs/optimized/eb0f70f7qg0lwhfftqxruwlu9.ll
33 39 bench/zed-rs/optimized/epuo8yz105556scsed5wrqb4z.ll

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github-actions bot commented Apr 4, 2025

Here's a high-level summary of the major changes in this LLVM IR patch:

  1. Addition of !range Metadata:

    • Many load instructions now include an additional !range metadata, which provides information about the valid range of values for the loaded variable. This can help with optimizations by allowing the compiler to make assumptions about possible values.
    • Example: %.pr = load i64, ptr %4, align 8, !range !35

  2. Unreachable Block Changes:

    • Several unreachable blocks have been removed or their predecessors have been updated. This simplifies control flow and removes dead code paths.
    • Example: default.unreachable: preds = %"_ZN6diesel13query_builder8ast_pass17AstPass$LT$DB$GT$8push_sql17hfab71232e8b34e69E.exit", %23

  3. Switch Instruction Updates:

    • Switch instructions have been modified to use the new default.unreachable block as the default destination instead of specific labels. This centralizes error handling and reduces redundancy.
    • Example: switch i64 %.val.pr.i.i, label %default.unreachable

  4. Metadata Reordering and Renaming:

    • Some metadata entries have been reordered or renamed, likely to better reflect their relationships or to improve clarity.
    • Example: !2162 = !{i8 0, i8 14} vs !2162 = !{i64 1}

  5. Comparison Operator Changes:

    • A few comparison operations have been updated from icmp ult (unsigned less-than) to icmp samesign ult (signed less-than with same sign). This ensures that the comparison respects the signedness of the operands, potentially leading to more accurate optimizations.
    • Example: %switch = icmp samesign ult i64 %37, 2

These changes collectively aim to improve code generation by providing more precise information to the optimizer, simplifying control flow, and ensuring correctness in comparisons. The addition of !range metadata is particularly noteworthy as it can enable further optimizations by reducing the number of potential values the compiler must consider for certain variables.

model: qwen-plus-latest
CompletionUsage(completion_tokens=481, prompt_tokens=109757, total_tokens=110238, completion_tokens_details=None, prompt_tokens_details=None)

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