Labels

Something isn't working and no workaround

Deferred until after current Redesign Project

Pull requests that update a dependency file

Improvements or additions to documentation

This issue or pull request already exists

Engineering change order (post-PnR)

New feature or request

Something isn't working

Makefile or in-repository flow script changed

Good for newcomers

Extra attention is needed

This doesn't seem right

Gate level verilog and/or layout changed

Issues related to precheck

Further information is requested

Verilog source code changed

Added or changed timing files

Verilog testbenches and simulation

This will not be worked on

Error is in a different repository