DSPHDL

Introduction

This project aims to use VHDL for Digital Signal Processing (DSP) applications. In this repo, we will learn how to generate some prevalent modulations. You can download the whole project from repository and try your desired setting (e.g. output frequency, bit-width, etc.).
For more information on Phase-shift keying please visit here, and for LFM (Linear Frequency Modulation) here.

Prerequisites

Xilinx ISE, ModelSim SE, Vivado softwares

BPSK and QPSK Outputs of ISE

By running the BPSK project, you will see results similar to Fig.1

And by running the QPSK project, the result will be similar to Fig.2

BPSK and QPSK Outputs of Vivado

Please pay attention:

• My Vivado version was 2021.1.
• After the project folder is created from the tcl file, copy the "BPSK_Selector_21" folder to it.
• To prevent confusion, it is recommended to run the TCL file "section by section" in TCL Console.
• Location addresses of files may be different from yours.
• The PC configuration may be different from yours (Mine had 12 cores).

By running the .tcl file, you will have a Bock Design similar to the:

If you finish the stages in order, you will see the following simulation:

LFM Outputs of Vivado

By running the BPSK project, you will see results similar to this:

NB: If you find this project useful, I would appreciate it if you cite this page and give it a star :)