Multi-FPGA Integration

[bwintermann]

In this (draft) PR I will slowly add all components required for enabling Multi-FPGA inference. This will mostly be additions and new transformations with the exception of vitis_build.py which needs to be changed almost entirely.

The goal is to keep compatibility to the existing flow so that no changes whatsoever are required to execute FINN as one does usually. Configuration will be done via the existing BuildDataflowConfig. Metadata and node attribute assignments will be named and used as general as possible so that eventual changes or additional ways to utilize multiple FPGAs can be integrated without issue.

[bwintermann]

The following things have to be ported from my private repo to here to enable Multi-FPGA:

• The partitioning transformation that assigns the device id of a given node
• Adding the communication kernels as a dependency
• (Optionally) The SLR assignment transformation that assigns the SLR of a given node based on some constraints
• New CreateStreamingDataflowPartition function that considers device ID (+ optionally SLR?)
• Aurora packing transformation
• Network metadata management transformation and classes
• The Vitis packaging transformation for the Multi-FPGA communication kernels
• Multi-FPGA VitisBuild
• Add DDR / HBM to considered_resources too
• Multi-FPGA Linking Config creation
• Parallel synthesis
• Label and move bitstreams and synthesis reports to the output directory

Final Checks before Merging

• Remove any changes done to logging, infrastructure, etc. that are not part of main/dev
• Merge Multi-FPGA VitisBuild with Single-FPGA (work from Improving VitisBuild #27 continues here until we merge to dev)
• Improve naming (unique, short and concise names)
• Remove all open TODOs in the PR
• Check Test coverage and pass-rate

Additional features:

• Nicer graph manipulation (see Adding graph utility functions #26) (Postponed for now, see ONNX Script)
• Enable usage of existing Floorplanning transformation instead of CreateSDP
• Give option to choose between our and finn-experimentals partitioner?
• Maybe give option to automatically change to LUTRAM if resources left over
• Automatic calculation of the required number of FPGAs
• (At some point) Integration of end2end Multi-FPGA tests into CI?

Will be part of a different PR:

• Integration-readiness: Output metadata required for SLURM interaction and usage of the fast C++ driver https://github.com/eki-project/finn-cpp-driver