Improve SVE2 optimizations of Gemm32fNN - #830
Merged
Merged
Conversation
Rewrite SimdSve2Gemm32fNN microkernels in explicit NEON/AVX-512BW style: remove SIMD_SVE2_GEMM_* macros, use unpredicated svmla_f32_x on full vector panels, add 1/2/3/4-panel N kernels, B-first FMLA order for the 6-row kernels, and L1/L2/L3 cache blocking. Document under release 7.2.165. Co-authored-by: Ihar Yermalayeu <ermig1979@gmail.com>
ermig1979
marked this pull request as ready for review
August 6, 2026 14:09
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Improves ARM SVE/SVE2 optimizations of
SimdGemm32fNNinSimdSve2Gemm32fNN.cppand documents the change under release 7.2.165.Changes
SIMD_SVE2_GEMM_*macros; expand microkernels to explicit code matching the NEON/AVX-512BW / Gemm32fNT style.svmla_f32_xon full-vector N panels; keep maskedsvmla_f32_monly for the N remainder.Kernel6x4nnloads B first, then streams A rows).docs/2026.html(release 7.2.165 Algorithms → Improving).Validation
./Test "-r=.." -fi=Gemm32fNN -tt=1 -ts=1— passed.-DSIMD_SVE2=ON:Simd::Sve2::Gemm32fNNlinked inlibSimd.so.-cpu max,sve=on, VL=512):Gemm32fNNAutoTest passed for Base/NEON/SVE2.M/Nshapes (remainder panels) passed under QEMU at SVE VL=128/256/512.