Add Xilinx XPM_MEMORY_SPRAM primitive

[Sergeant-Salz]

Xilinx provides a set of macros (XPM - Xilinx Parameterizeable Macros) for instantiating memory blocks on FPGA.
These provide more configurability than automatically inferred memory.

This change implements a wrapper for the Single Port RAM macro XPM_MEMORY_SPRAM with a BRAMServer interface. Other variants can be added easily based on this template. It is possible to implement byte enabled variants, multi port RAMs, ROMs and more.

[Sergeant-Salz]

Example use of how a BRAM instance with 1024x 32bit words and a read latency of 1 cycle is created. Additionally, memory values are initialized to the data in "meminit.mem" during simulation (file needs to be part of the Vivado project)

    // Concrete parameter sizes for testing
    XPMMemConfig memconfig = XPMMemConfig {
        memType:        BRAM,
        memSizeWords:   1024,
        readLatency:    1,
        memoryInitFile: tagged File "meminit.mem"
    };

    // Instantiate the DUT
    BRAMServer#(Bit#(16), Bit#(32)) dut <- mkSPRAM(memconfig);