esa-tu-darmstadt · PetrifiedPanda · Jun 24, 2026 · Jun 24, 2026 · Jun 24, 2026 · Jun 24, 2026
diff --git a/docs/ConversionPasses.md b/docs/ConversionPasses.md
@@ -15,6 +15,10 @@ The YAML is consumed by the Python patch generator (gen_patches.py).
 -output : Output path for the YAML analysis file
 ```
 
+### `-coredsl-explode-struct-registers`
+
+_Divide struct registers into multiple scalar registers_
+
 ### `-coredsl-legalize-cf`
 
 _Legalize cf operations by converting them to scf_

diff --git a/docs/CoreDSLDialect.md b/docs/CoreDSLDialect.md
@@ -491,7 +491,7 @@ Examples:
 
 | Result | Description |
 | :----: | ----------- |
-| `result` | an arbitrary precision integer with signedness semantics |
+| `result` | any type |
 
 
 
@@ -728,7 +728,7 @@ coredsl.set @MEM[%addr : ui32, 0:3] = %3 : ui32 // big-endian
 | Operand | Description |
 | :-----: | ----------- |
 | `base` | an arbitrary precision integer with signedness semantics and unsigned integer |
-| `value` | an arbitrary precision integer with signedness semantics |
+| `value` | any type |
 
 
 

diff --git a/include/shortnail/Conversion/Passes.td b/include/shortnail/Conversion/Passes.td
@@ -74,6 +74,14 @@ def CoreDSLLegalizeCF : Pass<"coredsl-legalize-cf", "::mlir::coredsl::ISAXOp"> {
   ];
 }
 
+def CoreDSLExplodeStructRegisters : Pass<"coredsl-explode-struct-registers", "::mlir::coredsl::ISAXOp"> {
+  let summary = "Divide struct registers into multiple scalar registers";
+  let dependentDialects = [
+    "::mlir::coredsl::CoreDSLDialect",
+    "::circt::hw::HWDialect",
+  ];
+}
+
 def AnalyzeISAX : Pass<"analyze-isax", "mlir::ModuleOp"> {
   let summary = "Analyze CoreDSL ISAX MLIR and output structured YAML";
   let description = [{

diff --git a/include/shortnail/Dialect/CoreDSL/CoreDSL.td b/include/shortnail/Dialect/CoreDSL/CoreDSL.td
@@ -98,6 +98,7 @@ def CoreDSL_Dialect : Dialect {
       "comb::CombDialect",
     ];
     let cppNamespace = "::mlir::coredsl";
+    let hasCanonicalizer = 1;
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/include/shortnail/Dialect/CoreDSL/CoreDSLInterfaces.td b/include/shortnail/Dialect/CoreDSL/CoreDSLInterfaces.td
@@ -43,7 +43,7 @@ def GetSetOpInterface : OpInterface<"GetSetOpInterface"> {
     InterfaceMethod<
         "Get the minimal required index width.", "unsigned", "getMinIndexWidth">,
     InterfaceMethod<
-        "Get the underlying element type of the memory.", "::mlir::IntegerType",
+        "Get the underlying element type of the memory.", "::mlir::Type",
         "getElementType">
   ];
 }

diff --git a/include/shortnail/Dialect/CoreDSL/CoreDSLOps.h b/include/shortnail/Dialect/CoreDSL/CoreDSLOps.h
@@ -26,7 +26,7 @@ struct MemInfo {
   uint64_t size;
   unsigned maxIdxWidth;
   unsigned minIdxWidth;
-  IntegerType elementType;
+  Type elementType;
   bool isConst;
   bool isVolatile;
 };

diff --git a/include/shortnail/Dialect/CoreDSL/CoreDSLOps.td b/include/shortnail/Dialect/CoreDSL/CoreDSLOps.td
@@ -332,7 +332,7 @@ class CoreDSL_AccessOp<string mnemonic, string lhsAssemblyFormat, string rhsAsse
 
 def CoreDSL_GetOp : CoreDSL_AccessOp<"get", "$sym", "`:` type($result) attr-dict",
                                     (ins FlatSymbolRefAttr:$sym), 
-                                    (outs HWArithIntegerType:$result),
+                                    (outs AnyType:$result),
                                     /*extraClassDecls=*/"Operation* resolveSymbol(); std::optional<MemInfo> getMemInfo();",
                                     /*isRangeAccessOptional=*/"true"> {
   let summary = "Reads from architectural state.";
@@ -358,7 +358,7 @@ def CoreDSL_GetOp : CoreDSL_AccessOp<"get", "$sym", "`:` type($result) attr-dict
 }
 
 def CoreDSL_SetOp : CoreDSL_AccessOp<"set", "$sym", "`=` $value `:` type($value) attr-dict",
-                                    (ins FlatSymbolRefAttr:$sym, HWArithIntegerType:$value), 
+                                    (ins FlatSymbolRefAttr:$sym, AnyType:$value),
                                     (outs), /*extraClassDecls=*/"Operation* resolveSymbol(); std::optional<MemInfo> getMemInfo();",
                                     /*isRangeAccessOptional=*/"true", [],
                                     /*folderPrototype=*/"LogicalResult $cppClass::fold(FoldAdaptor adaptor, SmallVectorImpl<OpFoldResult> &results)",

diff --git a/lib/Conversion/CMakeLists.txt b/lib/Conversion/CMakeLists.txt
@@ -1,4 +1,5 @@
 add_subdirectory(AnalyzeISAX)
+add_subdirectory(CoreDSLExplodeStructRegisters)
 add_subdirectory(CoreDSLLegalizeCF)
 add_subdirectory(CoreDSLToPy)
 add_subdirectory(MergeISAX)
diff --git a/lib/Conversion/CoreDSLExplodeStructRegisters/CMakeLists.txt b/lib/Conversion/CoreDSLExplodeStructRegisters/CMakeLists.txt
@@ -0,0 +1,14 @@
+add_shortnail_library(ShortnailCoreDSLExplodeStructRegisters
+    CoreDSLExplodeStructRegisters.cpp
+
+    DEPENDS
+    MLIRConversionPassIncGen
+
+    LINK_LIBS PUBLIC
+    MLIRIR
+    MLIRPass
+
+    CIRCTHW
+
+    ShortnailCoreDSL
+)