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[RISCV][ESP32P4] Fix ESPV builtin feature gating and intrinsic tests
Allow ESPVM masked builtins and esp_zero_xacc under +xespv or +xespv1v. Update esp32p4 Clang CodeGen FileCheck lines for current IR attributes. Co-authored-by: Cursor <cursoragent@cursor.com>
1 parent 6d18f79 commit dd74b6c

9 files changed

Lines changed: 37 additions & 36 deletions

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‎clang/include/clang/Basic/BuiltinsRISCVESPV.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -262,6 +262,7 @@ def esp_vzipt_16 : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)"
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def esp_vzipt_8 : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
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def esp_zero_q : RISCVBuiltin<"void(unsigned int)">;
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def esp_zero_qacc : RISCVBuiltin<"void()">;
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let Features = "xespv|xespv1v" in
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def esp_zero_xacc : RISCVBuiltin<"void()">;
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def esp_fft_ams_s16_ld_incp : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)">;
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def esp_fft_ams_s16_ld_incp_uaup : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)">;

‎clang/include/clang/Basic/BuiltinsRISCVESPVM.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11

2-
let Features = "xespv", Attributes = [NoThrow, RequiredVectorWidth<128>] in
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let Features = "xespv|xespv1v", Attributes = [NoThrow, RequiredVectorWidth<128>] in
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{
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// ESP.VCMULAS.S16.QACC.H (_m version)
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// Explicit state passing: Input QACC_H (2x128-bit), Output QACC_H (2x128-bit) via pointers
@@ -1417,7 +1417,7 @@ let Features = "xespv", Attributes = [NoThrow, RequiredVectorWidth<128>] in
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}
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// GPR ALU (.m): SSA result = op(rs1, rs2); lowers to esp.{addx2,addx4,subx2,subx4}.
1420-
let Features = "xespv", Attributes = [NoThrow] in {
1420+
let Features = "xespv|xespv1v", Attributes = [NoThrow] in {
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def esp_addx2_m : RISCVBuiltin<"unsigned int(unsigned int, unsigned int)">;
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def esp_addx4_m : RISCVBuiltin<"unsigned int(unsigned int, unsigned int)">;
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def esp_subx2_m : RISCVBuiltin<"unsigned int(unsigned int, unsigned int)">;
@@ -1427,7 +1427,7 @@ let Features = "xespv", Attributes = [NoThrow] in {
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// MOVX - Read/Write implicit registers (_m version)
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// These are scalar instructions, so they don't need RequiredVectorWidth<128>
1430-
let Features = "xespv", Attributes = [NoThrow] in {
1430+
let Features = "xespv|xespv1v", Attributes = [NoThrow] in {
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// ZERO.XACC - Zero XACC accumulator
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// Returns: i64 (XACC value, low 40 bits are zero)
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// ESP.ZERO.XACC (_m version) - Mixed model: XACC as {unsigned int low, unsigned int high}

‎clang/test/CodeGen/RISCV/esp32p4-intrinsics/riscv-esp32p4-bitwise.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// Test IR generation (Builtin -> Intrinsic)
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// RUN: %clang_cc1 -internal-isystem %S/../../../../lib/Headers -triple riscv32 -target-feature +xespv1v -emit-llvm -O1 -o - %s \
4-
// RUN: | FileCheck --check-prefixes=CHECK,PIE21 %s
4+
// RUN: | FileCheck %s
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// RUN: %clang_cc1 -internal-isystem %S/../../../../lib/Headers -triple riscv32 -target-feature +xespv -emit-llvm -O1 -o - %s \
6-
// RUN: | FileCheck --check-prefixes=CHECK,PIE22 %s
6+
// RUN: | FileCheck %s
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88

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#include <riscv_esp32p4.h>

‎clang/test/CodeGen/RISCV/esp32p4-intrinsics/riscv-esp32p4-fft.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ esp_vld_res_t res_qw;
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// FFT.AMS.S16.ST.INCP
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// CHECK-LABEL: define dso_local void @test_fft_ams_s16_st_incp_m(
165-
// CHECK-SAME: ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP2:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP3:%.*]], ptr noundef [[DST:%.*]], ptr noundef [[RS2:%.*]]) local_unnamed_addr #[[ATTR0]] {
165+
// CHECK-SAME: ptr noundef readonly captures(none) dead_on_return [[TMP0:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP1:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP2:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP3:%.*]], ptr noundef [[DST:%.*]], ptr noundef [[RS2:%.*]]) local_unnamed_addr #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[QX:%.*]] = load <8 x i16>, ptr [[TMP0]], align 16, !tbaa [[TBAA10:![0-9]+]]
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// CHECK-NEXT: [[QY:%.*]] = load <8 x i16>, ptr [[TMP1]], align 16, !tbaa [[TBAA10]]
@@ -236,7 +236,7 @@ esp_vld_res_t res_qy;
236236

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// FFT.CMUL.S16.ST.XP
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// CHECK-LABEL: define dso_local void @test_fft_cmul_s16_st_xp_m(
239-
// CHECK-SAME: ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP2:%.*]], ptr noundef [[DST:%.*]], ptr noundef [[RS2:%.*]]) local_unnamed_addr #[[ATTR0]] {
239+
// CHECK-SAME: ptr noundef readonly captures(none) dead_on_return [[TMP0:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP1:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP2:%.*]], ptr noundef [[DST:%.*]], ptr noundef [[RS2:%.*]]) local_unnamed_addr #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[QX:%.*]] = load <8 x i16>, ptr [[TMP0]], align 16, !tbaa [[TBAA10]]
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// CHECK-NEXT: [[QY:%.*]] = load <8 x i16>, ptr [[TMP1]], align 16, !tbaa [[TBAA10]]
@@ -255,7 +255,7 @@ void test_fft_cmul_s16_st_xp_m(esp_vec128_16_t Qx, esp_vec128_16_t Qy, esp_vec12
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// FFT.VST.R32.DECP
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// CHECK-LABEL: define dso_local void @test_fft_vst_r32_decp_m(
258-
// CHECK-SAME: ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr noundef [[DST:%.*]]) local_unnamed_addr #[[ATTR0]] {
258+
// CHECK-SAME: ptr noundef readonly captures(none) dead_on_return [[TMP0:%.*]], ptr noundef [[DST:%.*]]) local_unnamed_addr #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[QU:%.*]] = load <16 x i8>, ptr [[TMP0]], align 16, !tbaa [[TBAA10]]
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// CHECK-NEXT: [[TMP1:%.*]] = tail call ptr @llvm.riscv.esp.fft.vst.r32.decp.m(<16 x i8> [[QU]], ptr [[DST]], i32 0)

‎clang/test/CodeGen/RISCV/esp32p4-intrinsics/riscv-esp32p4-load-store-1.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// Test IR generation (Builtin -> Intrinsic)
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// RUN: %clang_cc1 -internal-isystem %S/../../../../lib/Headers -triple riscv32 -target-feature +xespv1v -emit-llvm -O1 -o - %s \
4-
// RUN: | FileCheck --check-prefixes=CHECK,PIE21 %s
4+
// RUN: | FileCheck %s
55
// RUN: %clang_cc1 -internal-isystem %S/../../../../lib/Headers -triple riscv32 -target-feature +xespv -emit-llvm -O1 -o - %s \
6-
// RUN: | FileCheck --check-prefixes=CHECK,PIE22 %s
6+
// RUN: | FileCheck %s
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#include <stdint.h>
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#include <riscv_esp32p4.h>

‎clang/test/CodeGen/RISCV/esp32p4-intrinsics/riscv-esp32p4-movx-r-w-sar.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -852,7 +852,7 @@ void test_fft_ams_s16_ld_incp_uaup_with_sar(void *src, void *qu_out, void *qz_ou
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// ESP.FFT.AMS.S16.ST.INCP test with explicit SAR state passing
854854
// CHECK-LABEL: define dso_local void @test_fft_ams_s16_st_incp_with_sar(
855-
// CHECK-SAME: ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP2:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP3:%.*]], ptr noundef [[DST:%.*]], ptr noundef [[RS2:%.*]], ptr noundef writeonly captures(none) initializes((0, 16)) [[QZ_OUT:%.*]], i32 noundef [[SAR_VAL:%.*]]) local_unnamed_addr #[[ATTR2]] {
855+
// CHECK-SAME: ptr noundef readonly captures(none) dead_on_return [[TMP0:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP1:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP2:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP3:%.*]], ptr noundef [[DST:%.*]], ptr noundef [[RS2:%.*]], ptr noundef writeonly captures(none) initializes((0, 16)) [[QZ_OUT:%.*]], i32 noundef [[SAR_VAL:%.*]]) local_unnamed_addr #[[ATTR2]] {
856856
// CHECK-NEXT: [[ENTRY:.*:]]
857857
// CHECK-NEXT: [[QX:%.*]] = load <8 x i16>, ptr [[TMP0]], align 16, !tbaa [[TBAA10:![0-9]+]]
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// CHECK-NEXT: [[QY:%.*]] = load <8 x i16>, ptr [[TMP1]], align 16, !tbaa [[TBAA10]]
@@ -910,7 +910,7 @@ esp_vld_res_t res_qy;
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911911
// ESP.FFT.CMUL.S16.ST.XP test with explicit SAR state passing
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// CHECK-LABEL: define dso_local void @test_fft_cmul_s16_st_xp_with_sar(
913-
// CHECK-SAME: ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP2:%.*]], ptr noundef [[DST:%.*]], ptr noundef [[RS2:%.*]], i32 noundef [[SAR_VAL:%.*]]) local_unnamed_addr #[[ATTR2]] {
913+
// CHECK-SAME: ptr noundef readonly captures(none) dead_on_return [[TMP0:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP1:%.*]], ptr noundef readonly captures(none) dead_on_return [[TMP2:%.*]], ptr noundef [[DST:%.*]], ptr noundef [[RS2:%.*]], i32 noundef [[SAR_VAL:%.*]]) local_unnamed_addr #[[ATTR2]] {
914914
// CHECK-NEXT: [[ENTRY:.*:]]
915915
// CHECK-NEXT: [[QX:%.*]] = load <8 x i16>, ptr [[TMP0]], align 16, !tbaa [[TBAA10]]
916916
// CHECK-NEXT: [[QY:%.*]] = load <8 x i16>, ptr [[TMP1]], align 16, !tbaa [[TBAA10]]

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