esp-21.1.3_20260408

Features

• Added ESPV arithmetic support in Clang for add/sub/saturating operations.
  This introduces frontend and codegen handling for ESPV vector/scalar arithmetic forms, enabling Clang to recognize and lower these operations more reliably for ESP targets.

• Added ESPV load/store support in Clang.
  This extends Clang/backend integration to cover ESPV memory access operations so vector data movement can be emitted through supported ESPV instructions instead of generic fallbacks.

• Added ESPV intrinsic support for shift/src/qacc operations (src.q, srcmb, srcq, srcxxp, slcxxp, vsmulas, etc.).
  This broadens intrinsic coverage for DSP-style data path and accumulator workflows, making specialized shift/source/accumulate operations available from C/C++ intrinsics with proper lowering.

• Added RISC-V intrinsic support for movx-r-w-xacc.
  This enables explicit intrinsic-level access to XACC move semantics, improving programmability for advanced ESPV/RISC-V acceleration paths.

• Added ESPV intrinsic coverage for UA-state/XACC moves (e.g., movi and related ops).
  This fills gaps in intrinsic exposure for accumulator/state manipulation, helping developers write low-level optimized kernels without inline assembly.

• Added an opt-in switch for ESPV target lowering (disabled by default).
  This allows controlled rollout and safer experimentation: ESPV lowering can be enabled when needed while preserving existing default behavior for unaffected builds.

Fixes

• Fixed Xtensa handling of .set symbolic constants for b4const/b4constu immediates. Closes #124
• Fixed Xtensa lowering for trap/debugtrap operations. Closes #123
• Fixed object streamer setup by initializing subtarget info with CPU and target features in initializeRecordStreamer. Closes #122
• Fixed Xtensa lowering for setcc. Close #126
• Added ESP32-P4 workaround by disabling RISCVPushPopOpt and using non-reversed callee-saved register order.

esp-21.1.3_20260304

Changes since esp-20.1.1_20250829:

Features:

• Rebased on upstream LLVM 21.1.3.
• [Toolchain] Upgraded GNU binutils to v2.45.
• [Toolchain] Upgraded newlib to v4.5.0.
• [Toolchain] Upgraded libstdc++ and libgcc to 15.2.0.
• [Toolchain] Included LLVM runtime libraries: linunwind, libc++ and libc++-abi.
• [Toolchain] Separate distribution package for clangd.
• [RISCV] Defined Espressif CPUs. Now user can choose CPU with -mcpu option.
• [RISCV] Split xesppie to xespv for custom vector instructions and xesploop for HW loop instructions.
• [RISCV][ESPV] Implemented xespv 2.2 extension. Due to the lack of support for multiple versions of the same extension in LLVM old PIE v2.1 extension is supported as xespv1v.
• [RISCV][ESP32H4] Implemented support for custom dsp instructions in xespdsp extension.
• [RISCV] Predefine _GNU_SOURCE when compiling C++ sources in order to follow g++ convention.
• [Xtensa] Implemented WER/RER instructions.

Fixes:

• [Xtensa][ESP32S3] Fixed ESP32S3 user registers. Closes #120.
• [Toolchain][RISCV] Made compiler-rt default unwind library for RISCV.
• [RISCV][ESPV] Fix incorrect instruction scheduling with ESP intrinsics using indexed registers. Some ESP intrinsics used numeric API indices to represent hardware registers instead of explicit register operands. Because these indices were not visible to the scheduler as register dependencies, instruction scheduling could break the use-def chain when scheduling was enabled, potentially leading to incorrect code generation. The affected instructions are now treated as scheduling boundaries to prevent unsafe instruction reordering.
• [Xtensa] Fixed vararg lowering.
• [Xtensa] Fixed ConstantPool lowering. Implemented lowering of the aggregate and vector constants
  in Global Variables like it is done in GCC.
• [Xtensa] Improved asm inline parsing. Added support for a and d register constraints.

esp-20.1.1_20250829

Changes since esp-19.1.2_20250312:

Features:

• Rebased on upstream LLVM 20.1.1
• [Xtensa][MC] Added support for _bnez.n and _beqz.n alias instructions.
• [ESP32-P4][Pass] Added optimization pass which lowers memcpy to the optimized sequence of ESP32-P4 SIMD instructions.

Fixes:

• [Xtensa] Fixed VASTART lowering. Regression in upstream Xtensa backend led to the incorrect variadic arguments passing on stack. The problem was caught in IDF application when code generated by GCC calls variable args function compiled by clang.
• [ESP32P4] Fixed vldbc.8.ip/vldbc.16.ip instructions immediate range. Correct step for immediate value in vldbc.8.ip is 1 and 2 for vldbc.16.ip.
• [Xtensa] Fixed duplicated CPI symbols with text section literals. Close #113.
• [Toolchain][Espressif] Synced runtime libs logic with baremetal toolchain class.

esp-19.1.2_20250312

Changes since esp-19.1.2_20250225:

Fixes:

• [Espressif] Replaced esp-helper script with esp-clang-libs.info to keep version in standalone libs distro

esp-19.1.2_20250225

Changes since esp-19.1.2_20250211:

Fixes:

• [Clang] Fixed missed release tag in --version output

esp-19.1.2_20250211

Changes since esp-18.1.2_20240912:

Features:

• Upgraded to LLVM 19.1.2.
• [Clangd] Return Includes for documentSymbol request. This solves part of the problem related to missed includes in Outline view. Described here.
• [Xtensa] Added fp16 conversion support. It fixes #103 and #91.
• [Xtensa] Added +forced-atomics target feature support. Solves #105.
• [Toolchain] [Espressif] Upgraded libgcc and libstdc++ from GCC 14.2.0.
• [Toolchain] [Espressif] Upgraded GNU binutils version to 2.43.1.
• [Toolchain] [Espressif] [RISCV] Added Zcmt and Zcmp support to GNU binutils.
• [Toolchain] [Espressif] [RISCV] Added multilibs for Z-extensions (zba, zbb, zbc, zbs).
• [Toolchain] [Espressif] Added helper script to support versioning of standalone libraries distribution. Toolchain's distribution part of the solution for #108.
• [Toolchain] [Espressif] [ESP32P4] Added SplitLoopByLength, CustomLICM and LoopUnrollAndRemainder optimization passes to generate faster code for DSP function implementations like FIR, SQRT etc.

Fixes:
[Xtensa] Fixed issue appeared when allocating objects on stack with alignment more then 32 bytes. That could lead to unaligned address of objects accessed via pointer API.

• [Xtensa] Implement XtensaNullTargetStreamer. It fixes crash in Xtensa AsmParser::run() during ModuleSummaryIndexAnalysis pass.
• [Xtensa] Default to unsigned char. Align with GCC behaviour.
• [Xtensa] [ESP32S3] Fixed TIE format_32 encoding and disassembler ambiguities between x24 and format_32 encoding. llvm-objdump had a problem of determining whether it is x24 or format_32 instruction. format_32 encoding was wrong and now fixed to match the TRM.
• [Xtensa] [ESP32S3] Fixed verifier issues in instructions with INOUT operands. Without constraints -verify-machineinstrs failed. Also, without constraints llvm-objdump treated inout registers as 2 different operands which led objdump to think that an instruction had one extra argument.
• [Toolchain] [Espressif] [Newlib]: fix tgammaf(-inf) return value (espressif/esp-idf#14273)
• [Toolchain] [Espressif]: Mingw standalone libs distro contained binutils which should not be part of it.

esp-18.1.2_20240912

Changes since esp-18.1.2_20240829:

Fixes:

• [Xtensa] Fix atomic store operands order. In LLVM 18 atomic store operands order was changed https://reviews.llvm.org/D123143.

esp-18.1.2_20240829

Changes since esp-18.1.2_20240815:

Fixes:

• [RISCV] Fixed registers class for esp32p4 HW loop instructions. Removed unnecessary registers operands limits for HW loop instructions.
• [Toolchain][Espressif] Added 'xesppie' multilib variant mapping for esp32p4. Fixed warning: no multilib found matching flags when xesppie extension is enabled.
• [RISCV][ESP32P4] Don't yet consider v16i8 and v4i32 legal. W/o this fix Clang crashed when tried to select instruction for v16i8 and v4i32 types.

esp-18.1.2_20240815

Changes since esp-17.0.1_20240419:

Features:

• Upgraded LLVM ver to 18.1.2.
• [RISCV] Support for ESP32-P4 custom instructions in RISCV backend.
• [RISCV] Add support for user trap CSRs.
• [Xtensa] Added support for asm underscore prefix which prevents assembler from replacing instructions with their equivalents (single or multiple instructions) when it is applicable.

esp-17.0.1_20240419

Changes (since esp-17.0.1_20240408):

Fixes:

• [Xtensa] Fix issue with adding scavenging frame index. Fixes bug introduced in 50f918b which led to missed spill slot and error like LLVM ERROR: Error while trying to spill A9 from class AR: Cannot scavenge register without an emergency spill slot!.
• [Toolchain][Espressif] Include clangd into distribution. Close #93