v0.12.0-esp32-20251215

v0.12.0-esp32-20251215

Features:

• Added automatic ROM revision detection for ESP32-P4, supporting hardware rev3 (ECO5) and earlier revisions.
• Added missing CSR registers for ESP32-P4 with generic custom register access implementation.
• Added LP core debugging support for ESP32-P4 and ESP32-C5
• Added single core debugging support for ESP32-P4 and ESP32-H4
• Added warning for potential misconfiguration when config variables are set on command line in the wrong order
• Added openocd_feature_flags_ide metadata to esp-config.json to allow IDEs to detect OpenOCD capability flags without parsing version strings.
• Added fast non-intrusive JTAG profile sampler for ESP32 and ESP32-S2, providing over 1000x performance improvement compared to the previous approach. #357

Fixes:

• Fixed user counter access in user mode by implementing the workaround in target code, enabling register access from GDB.
• Fixed unaligned memory read issue on Xtensa targets where retry attempts incorrectly applied buffer offset twice, causing memory to be read from the wrong address (e.g., 0x4 instead of 0x2).
• Added missing ESP32-C61 target to the Espressif board detection script.
• Fixed several issues related to flash and RAM breakpoints.
• Fixed unnecessary memory protection check when flash support is disabled.
• Fixed flash access from stub when target is in download mode to avoid memory mapping issues.
• Improved apptrace read/write reliability by adding a recovery mechanism that halts the target for a final attempt when normal retries fail.
• Fixed several issues related to ESP32-H4
• Increased algorithm timeout for compressed writes to handle binaries with high compression ratios, where the default 3-second timeout was insufficient. espressif/vscode-esp-idf-extension#1708
• Fixed semihosting issues on RISC-V targets: dcsr.ebrakxxx bits now persist correctly after unexpected resets, and WDTs are properly disabled during semihosting operations.
• Fixed thread awareness support for Zephyr RTOS on RISC-V and Xtensa targets.

Other:

• Synced with upstream up to commit 22afaae
• Enabled minimal register save/restore for algorithms to improve performance.