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335 | 335 | #define ECID2 926 |
336 | 336 | #define ECID3 927 |
337 | 337 |
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338 | | -#define MSR_LE 0x00000001 |
339 | | -#define MSR_RI 0x00000002 |
340 | | -#define MSR_PM 0x00000004 |
341 | | -#define MSR_DR 0x00000010 |
342 | | -#define MSR_IR 0x00000020 |
343 | | -#define MSR_IP 0x00000040 |
344 | | -#define MSR_FE1 0x00000100 |
345 | | -#define MSR_BE 0x00000200 |
346 | | -#define MSR_SE 0x00000400 |
347 | | -#define MSR_FE0 0x00000800 |
348 | | -#define MSR_ME 0x00001000 |
349 | | -#define MSR_FP 0x00002000 |
350 | | -#define MSR_PR 0x00004000 |
351 | | -#define MSR_EE 0x00008000 |
352 | | -#define MSR_ILE 0x00010000 |
353 | | -#define MSR_POW 0x00040000 |
| 338 | +#define MSR_LE 0x00000001 |
| 339 | +#define MSR_RI 0x00000002 |
| 340 | +#define MSR_PM 0x00000004 |
| 341 | +#define MSR_DR 0x00000010 |
| 342 | +#define MSR_IR 0x00000020 |
| 343 | +#define MSR_IP 0x00000040 |
| 344 | +#define MSR_FE1 0x00000100 |
| 345 | +#define MSR_BE 0x00000200 |
| 346 | +#define MSR_SE 0x00000400 |
| 347 | +#define MSR_FE0 0x00000800 |
| 348 | +#define MSR_ME 0x00001000 |
| 349 | +#define MSR_FP 0x00002000 |
| 350 | +#define MSR_PR 0x00004000 |
| 351 | +#define MSR_EE 0x00008000 |
| 352 | +#define MSR_ILE 0x00010000 |
| 353 | +#define MSR_POW 0x00040000 |
| 354 | + |
| 355 | +#define THRM1_TIN 0x80000000 |
| 356 | +#define THRM1_TIV 0x40000000 |
| 357 | +#define THRM1_THRESHOLD_MASK 0x3F800000 |
| 358 | +#define THRM1_THRESHOLD(n) (((n) << 23) & THRM1_THRESHOLD_MASK) |
| 359 | +#define THRM1_TID 0x00000004 |
| 360 | +#define THRM1_TIE 0x00000002 |
| 361 | +#define THRM1_V 0x00000001 |
| 362 | + |
| 363 | +#define THRM2_TIN THRM1_TIN |
| 364 | +#define THRM2_TIV THRM1_TIV |
| 365 | +#define THRM2_THRESHOLD_MASK THRM1_THRESHOLD_MASK |
| 366 | +#define THRM2_THRESHOLD(n) THRM1_THRESHOLD(n) |
| 367 | +#define THRM2_TID THRM1_TID |
| 368 | +#define THRM2_TIE THRM1_TIE |
| 369 | +#define THRM2_V THRM1_V |
| 370 | + |
| 371 | +#define THRM3_CALIBRATION_MASK 0x3E000000 |
| 372 | +#define THRM3_CALIBRATION(x) (((x) << 25) & THRM3_CALIBRATION_MASK) |
| 373 | +#define THRM3_SITV_MASK 0x00003FFE |
| 374 | +#define THRM3_SITV(n) (((n) << 1) & THRM3_SITV_MASK) |
| 375 | +#define THRM3_E 0x00000001 |
354 | 376 |
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355 | 377 | #define PPC_ALIGNMENT 8 |
356 | 378 |
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