feat(rvv): add RVV kernels for fvec_add/fvec_sub and PQ dsub=2 distance tables - #5601
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feat(rvv): add RVV kernels for fvec_add/fvec_sub and PQ dsub=2 distance tables#5601ihb2032 wants to merge 1 commit into
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…ce tables RISC-V builds dispatch fvec_add, fvec_sub and compute_PQ_dis_tables_dsub2 through with_simd_level_256bit, whose mask has no RISCV_RVV bit, so they fall back to the scalar NONE implementation. - Add native vector-length-agnostic RVV kernels (vsetvl-based, m8) for fvec_add, fvec_sub and compute_PQ_dis_tables_dsub2; each product/square is rounded before the final add so results stay bit-identical to scalar - Route the four dispatchers through the new AVAILABLE_SIMD_LEVELS_A0_NO_AVX512 mask so RISC-V hosts use the RVV kernels - Enable the PQ dsub=2 distance table path in ProductQuantizer on RISC-V, previously guarded to AVX2/ARM_NEON only Measured on SG2044 (64-core RISC-V, RVV 1.0), rcq-search: instructions -5.2%, cycles -6.5%, wall time -6.1%; fvec_add hotspot drops from 1.06% to 0.18% of perf samples. sq-accuracy reconstruction errors bit-identical. Co-authored-by: lyd1992 <liuyudong@iscas.ac.cn> Co-authored-by: ww8191201-coder <wanghongyan2025@iscas.ac.cn> Co-authored-by: YuanSheng <yuansheng@isrc.iscas.ac.cn>
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Summary
On RISC-V,
fvec_add,fvec_subandcompute_PQ_dis_tables_dsub2are dispatched throughwith_simd_level_256bit, whose level mask (AVAILABLE_SIMD_LEVELS_AVX2_NEON) has noRISCV_RVVbit. RVV hosts therefore fall back to the scalar NONE implementation.This PR adds native RVV kernels for these functions and fixes the dispatch, following the same vector-length-agnostic approach as the RVV kernels already in the tree: the kernels are
__riscv_vsetvl-based (m8) and adapt to any VLEN at runtime instead of assuming a fixed vector width.Changes
faiss/utils/simd_impl/distances_rvv.cpp:fvec_add(vector + vector and vector + scalar)fvec_subcompute_PQ_dis_tables_dsub2(PQ distance tables for dsub = 2, both L2 and inner product). Each product/square is rounded before the final add — like the NONE implementation and unlike a fusedvfmacc— so the tables are bit-identical to the scalar ones.AVAILABLE_SIMD_LEVELS_A0_NO_AVX512mask infaiss/impl/simd_dispatch.h(A0 minus AVX512: functions with NONE/AVX2/ARM_NEON/RISCV_RVV implementations but no 512-bit specialization, so AVX512 machines keep the AVX2 path).faiss/utils/distances_dispatch.hthrough the new mask.ProductQuantizer::compute_distance_tables/compute_inner_prod_tableson RISC-V (COMPILE_SIMD_RISCV_RVV), previously guarded to AVX2/ARM_NEON only. No behavior change on other platforms.Performance
Measured on SG2044 (64-core RISC-V, RVV 1.0), Faiss C++ benchmark suite, rcq-search case:
fvec_addhotspot in perf record drops from 1.06% (scalar NONE) to 0.18% (RVV) of samples.Correctness
sq-accuracyreconstruction errors bit-identical to baseline on all 9 quantizer types,ndiff_for_idempotence=0.compute_PQ_dis_tables_dsub2kernel is bit-identical to the scalar implementation by construction (no fused multiply-add).