The primary goal of this lab project was to design and implement a processor using the knowledge gained from our Digital Systems class. We constructed the necessary components, such as combinational and sequential circuits, to achieve this. These components included an Arithmetic and Logic Unit (ALU), two latches, and a control unit consisting of a Finite State Machine (FSM) and a 4:16 decoder that manages state transitions. The FSM employed Moore's logic to control operations. This processor executes various tasks on two 8-bit inputs, with control signals from the FSM and a 16-bit output from the decoder. The results were displayed on connected 7-segment displays and analyzed through waveform outputs.
ALU: The ALU performs a variety of operations based on the signals received from the FSM and decoder. The inputs to the ALU include the clock signal, A, B, OP, and a Student ID. The ALU selects an operation based on the OP signal and executes it on the rising edge of the clock. The outputs of the ALU are Neg, R1, and R2. R1 represents the first 4 bits of the 8-bit result, while R2 represents the remaining 4 bits. Together, these outputs display the full 8-bit result. The Neg output sends a signal to the 7-segment display when a negative result is required.
7-Segment Display: The 7-segment display converts the binary output from the ALU into a readable format. It is capable of displaying decimal values from 0 to 15, as well as hexadecimal values. The display is also programmed to indicate negative results when needed. Throughout the lab, multiple 7-segment displays were used to present the ALU's output.
4:16 Decoder: The 4:16 decoder converts a 4-bit input signal from the FSM into a 16-bit microcode output. When connected to the FSM, the decoder plays a critical role in determining and controlling the operations that the processor will execute.
FSM: The FSM, part of the control unit in this lab, cycles through nine states, implementing a Moore machine. On the rising edge of the clock, when data-in is enabled, the FSM transitions through states S0 to S8. After reaching S8, the FSM returns to S0. The primary function of the FSM is to send state changes to the 4:16 decoder, which in turn controls the sequence of operations for the processor.
Latches 1 and 2: The latches serve as storage devices, capturing and holding inputs A and B from the FPGA until the positive clock edge triggers them. These latches function as D latches, transferring the input data to the output. Two identical latches are used in this lab, one for each input, with the same code applied to both.