Time parallel RIDC and SDC #634
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connorjward
reviewed
May 15, 2025
| @@ -33,7 +33,7 @@ jobs: | |||
| GUSTO_PARALLEL_LOG: CONSOLE | |||
| PYOP2_CFLAGS: -O0 | |||
| # Make sure that tests with >4 processes are not silently skipped | |||
| PYTEST_MPI_MAX_NPROCS: 4 | |||
| PYTEST_MPI_MAX_NPROCS: 6 | |||
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This isn't sufficient. You also need to add extra - name: Run tests (nprocs = ???) steps below.
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Time parallel SDC and RIDC implementations. Splits SDC code into
deferred_correctionandparallel_dc. All should inherit from one overall DC class (Parallel_RIDC from RIDC and Parallel_SDC from SDC).Parallel SDC uses the diagonal preconditioners to compute solutions separately on each node, meaning we have M + 1 communicators.
Parallel RIDC pipelines the corrections, by having the number of nodes (M+1) being much greater than the number of corrections. It uses equispaced nodes on coarse intervals. Each correction (and the initial low order solution) are computed in parallel, meaning we have K + 1 communicators.
Serial RIDC has the reduced stencil and full stencil implementations, only the reduced stencil is used for Parallel RIDC.
The Firedrake Ensemble communicator is used for time parallelisation.