sdgemm micro-kernel for the SG2042 RISC-V processor

blis.pc

@@ -0,0 +1,11 @@
+prefix=/home/gceccolini/blis_sg2042
+exec_prefix=/home/gceccolini/blis_sg2042
+libdir=/home/gceccolini/blis_sg2042/lib
+includedir=/home/gceccolini/blis_sg2042/include
+
+Name: BLIS
+Description: BLAS-like Library Instantiation Software Framework
+Version: 0.9.0-180
+Libs: -L${libdir} -lblis
+Libs.private:  -lm -lpthread -latomic
+Cflags: -I${includedir}/blis

config/rvv_sg2042/bli_cntx_init_rvv_sg2042.c

@@ -0,0 +1,115 @@
+/*
+
+   BLIS
+   An object-based framework for developing high-performance BLAS-like
+   libraries.
+
+   Copyright (C) 2014, The University of Texas at Austin
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+    - Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    - Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    - Neither the name(s) of the copyright holder(s) nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include "../../kernels/rvv_sg2042/3/bli_rvv_sg2042_utils.h"
+
+void bli_cntx_init_rvv_sg2042( cntx_t* cntx )
+{
+	printf("!!!SONO LA NUOVA SUB-CONFIGURAZIONE!!!\n");
+	blksz_t blkszs[ BLIS_NUM_BLKSZS ];
+
+	// Set default kernel blocksizes and functions.
+	bli_cntx_init_rvv_sg2042_ref( cntx );
+
+	// -------------------------------------------------------------------------
+
+	// A reasonable assumptions for application cores is VLEN >= 128 bits, i.e.,
+	// v >= 4. Embedded cores, however, may implement the minimal configuration,
+	// which allows VLEN = 32 bits. Here, we assume VLEN >= 128 and otherwise
+	// fall back to the reference kernels.
+	const uint32_t v = get_vlenb() / sizeof(float);
+
+	if ( v >= 4 )
+	{
+		const uint32_t mr_s = 4 * v;
+		const uint32_t mr_d = 2 * v;
+		const uint32_t mr_c = 2 * v;
+		const uint32_t mr_z = v;
+
+		// TODO: Register different kernels based on the value
+		// of v to avoid MC becoming too big. (e.g. 2vx8)
+
+		// Update the context with optimized native gemm micro-kernels.
+		bli_cntx_set_ukrs
+		(
+		  cntx,
+
+		  // level-3
+		  BLIS_GEMM_UKR, BLIS_FLOAT,    bli_sgemm_rvv_sg2042_4vx4,
+		  BLIS_GEMM_UKR, BLIS_DOUBLE,   bli_dgemm_rvv_sg2042_4vx4,
+		  BLIS_GEMM_UKR, BLIS_SCOMPLEX, bli_cgemm_rvv_sg2042_4vx4,
+		  BLIS_GEMM_UKR, BLIS_DCOMPLEX, bli_zgemm_rvv_sg2042_4vx4,
+
+		  BLIS_VA_END
+		);
+
+		// Update the context with storage preferences.
+		bli_cntx_set_ukr_prefs
+		(
+		  cntx,
+
+		  // level-3
+		  BLIS_GEMM_UKR_ROW_PREF, BLIS_FLOAT,    FALSE,
+		  BLIS_GEMM_UKR_ROW_PREF, BLIS_DOUBLE,   FALSE,
+		  BLIS_GEMM_UKR_ROW_PREF, BLIS_SCOMPLEX, FALSE,
+		  BLIS_GEMM_UKR_ROW_PREF, BLIS_DCOMPLEX, FALSE,
+
+		  BLIS_VA_END
+		);
+
+		// Initialize level-3 blocksize objects with architecture-specific values.
+		//                                              s        d        c        z
+		bli_blksz_init_easy( &blkszs[ BLIS_MR ],     mr_s,    mr_d,    mr_c,    mr_z );
+		bli_blksz_init_easy( &blkszs[ BLIS_NR ],        4,       4,       4,       4 );
+		bli_blksz_init_easy( &blkszs[ BLIS_MC ],  20*mr_s, 20*mr_d, 60*mr_c, 30*mr_z );
+		bli_blksz_init_easy( &blkszs[ BLIS_KC ],      640,     320,     320,     160 );
+		bli_blksz_init_easy( &blkszs[ BLIS_NC ],     3072,    3072,    3072,    3072 );
+
+		// Update the context with the current architecture's register and cache
+		// blocksizes (and multiples) for native execution.
+		bli_cntx_set_blkszs
+		(
+		  cntx,
+
+		  // level-3
+		  BLIS_NC, &blkszs[ BLIS_NC ], BLIS_NR,
+		  BLIS_KC, &blkszs[ BLIS_KC ], BLIS_KR,
+		  BLIS_MC, &blkszs[ BLIS_MC ], BLIS_MR,
+		  BLIS_NR, &blkszs[ BLIS_NR ], BLIS_NR,
+		  BLIS_MR, &blkszs[ BLIS_MR ], BLIS_MR,
+
+		  BLIS_VA_END
+		);
+	}
+}

config/rvv_sg2042/bli_kernel_defs_rvv_sg2042.h

@@ -0,0 +1,42 @@
+/*
+
+   BLIS
+   An object-based framework for developing high-performance BLAS-like
+   libraries.
+
+   Copyright (C) 2022, The University of Texas at Austin
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+    - Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    - Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    - Neither the name(s) of the copyright holder(s) nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+//#ifndef BLIS_KERNEL_DEFS_H
+//#define BLIS_KERNEL_DEFS_H
+
+
+// -- REGISTER BLOCK SIZES (FOR REFERENCE KERNELS) ----------------------------
+
+
+//#endif

config/rvv_sg2042/make_defs.mk

@@ -0,0 +1,105 @@
+#
+#
+#  BLIS
+#  An object-based framework for developing high-performance BLAS-like
+#  libraries.
+#
+#  Copyright (C) 2014, The University of Texas at Austin
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are
+#  met:
+#   - Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#   - Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#   - Neither the name(s) of the copyright holder(s) nor the names of its
+#     contributors may be used to endorse or promote products derived
+#     from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#
+
+
+# Declare the name of the current configuration and add it to the
+# running list of configurations included by common.mk.
+THIS_CONFIG    := rvv_sg2042	
+#CONFIGS_INCL   += $(THIS_CONFIG)
+
+#
+# --- Determine the C compiler and related flags ---
+#
+
+# NOTE: The build system will append these variables with various
+# general-purpose/configuration-agnostic flags in common.mk. You
+# may specify additional flags here as needed.
+CPPROCFLAGS    := -DRISCV_SIZE=64
+
+#RISCV_ARCH     := $(shell $(CC) -DFORCE_RISCV_VECTOR -E build/detect/riscv/bli_riscv_detect_arch.h | grep '^[^\#]')
+#RISCV_ABI      := $(shell $(CC) -DFORCE_RISCV_VECTOR -E build/detect/riscv/bli_riscv_detect_abi.h | grep '^[^\#]')
+RISCV_ARCH	:= rv64gc_zfh_xtheadvector
+RISCV_ABI	:= lp64d
+
+ifeq (,$(findstring 64,$(RISCV_ARCH)))
+$(error The RISC-V compiler architecture $(RISCV_ARCH) is not compatible with $(THIS_CONFIG))
+else ifeq (,$(findstring 64,$(RISCV_ABI)))
+$(error The RISC-V compiler ABI $(RISCV_ABI) is not compatible with $(THIS_CONFIG))
+endif
+
+CMISCFLAGS     := -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
+CPICFLAGS      := -fPIC
+CWARNFLAGS     := -Wall -Wno-unused-function -Wfatal-errors
+
+# In case the A extension is not available
+LDFLAGS        += -latomic
+
+ifneq ($(DEBUG_TYPE),off)
+CDBGFLAGS      := -g
+endif
+
+ifeq ($(DEBUG_TYPE),noopt)
+COPTFLAGS      := -O0
+else
+COPTFLAGS      := -O2 -ftree-vectorize
+endif
+
+# Flags specific to optimized kernels.
+CKOPTFLAGS     := $(COPTFLAGS) -O3
+ifeq ($(CC_VENDOR),gcc)
+CKVECFLAGS     :=
+else
+ifeq ($(CC_VENDOR),clang)
+CKVECFLAGS     :=
+else
+$(error gcc or clang is required for this configuration.)
+endif
+endif
+
+# Flags specific to reference kernels.
+CROPTFLAGS     := $(CKOPTFLAGS)
+ifeq ($(CC_VENDOR),gcc)
+# Lower compiler optimization. cinvscalv fails at -O1
+CRVECFLAGS     := $(CKVECFLAGS) -O0
+else
+ifeq ($(CC_VENDOR),clang)
+CRVECFLAGS     := $(CKVECFLAGS) -funsafe-math-optimizations -ffp-contract=fast
+else
+CRVECFLAGS     := $(CKVECFLAGS)
+endif
+endif
+
+# Store all of the variables here to new variables containing the
+# configuration name.
+$(eval $(call store-make-defs,$(THIS_CONFIG)))

config_registry

@@ -55,12 +55,13 @@ power10:     power10
 power9:      power9
 bgq:         bgq
 
-# RISC-V architectures.
+# RISC-V architectures. Added!
 rv32i:       rv32i/rvi
 rv64i:       rv64i/rvi
 rv32iv:      rv32iv/rviv
 rv64iv:      rv64iv/rviv
-
+rvv_sg2042:  rvv_sg2042	
+
 # SiFive architectures.
 sifive_rvv: sifive_rvv
 sifive_x280: sifive_x280/sifive_rvv

frame/base/bli_arch.c

@@ -285,6 +285,9 @@ arch_t bli_arch_query_id_impl( void )
 		#ifdef BLIS_FAMILY_RV64IV
 		id = BLIS_ARCH_RV64IV;
 		#endif
+                #ifdef BLIS_FAMILY_RVV_SG2042	// added!
+                id = BLIS_ARCH_RVV_SG2042;
+                #endif
 
 		// SiFive microarchitectures.
 		#ifdef BLIS_FAMILY_SIFIVE_RVV
@@ -358,6 +361,7 @@ static const char* config_name[ BLIS_NUM_ARCHS ] =
     "rv64i",
     "rv32iv",
     "rv64iv",
+    "rvv_sg2042", // added!
 
     "sifive_rvv",
     "sifive_x280",

frame/include/bli_arch_config.h

@@ -277,7 +277,9 @@ INSERT_GENTCONF
 #ifdef BLIS_KERNELS_RVIV
 #include "bli_kernels_rviv.h"
 #endif
-
+#ifdef BLIS_KERNELS_RVV_SG2042
+#include "bli_kernels_rvv_sg2042.h"
+#endif
 // -- SiFive RISC-V architectures --
 
 #ifdef BLIS_KERNELS_SIFIVE_RVV

frame/include/bli_gentconf_macro_defs.h

@@ -219,7 +219,11 @@
 #else
 #define INSERT_GENTCONF_RV64IV
 #endif
-
+#ifdef BLIS_CONFIG_RVV_SG2042						// added!
+#define INSERT_GENTCONF_RVV_SG2042 GENTCONF( RVV_SG2042, rvv_sg2042 )
+#else
+#define INSERT_GENTCONF_RVV_SG2042
+#endif
 // -- SiFive architectures ----------------------------------------------------
 
 #ifdef BLIS_CONFIG_SIFIVE_RVV
@@ -284,6 +288,7 @@ INSERT_GENTCONF_RV32I \
 INSERT_GENTCONF_RV64I \
 INSERT_GENTCONF_RV32IV \
 INSERT_GENTCONF_RV64IV \
+INSERT_GENTCONF_RVV_SG2042 \
 \
 INSERT_GENTCONF_SIFIVE_RVV \
 INSERT_GENTCONF_SIFIVE_X280 \

frame/include/bli_type_defs.h

@@ -1005,6 +1005,7 @@ typedef enum
 	BLIS_ARCH_RV64I,
 	BLIS_ARCH_RV32IV,
 	BLIS_ARCH_RV64IV,
+	BLIS_ARCH_RVV_SG2042,	// added! 
 
 	// SiFive
 	BLIS_ARCH_SIFIVE_RVV,

include/blis.h

@@ -0,0 +1 @@
+#include <blis/blis.h>

include/cblas.h

@@ -0,0 +1 @@
+#include <blis/cblas.h>