feat: Thor (SM110) portable SIMT fallbacks, benchmark memory guard, and validation docs - #9
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…or SM110 The SM100-family CUTLASS 4.0 megakernel uses tcgen05/TMA descriptor paths that assert at runtime on sm_110a (Thor). Add a block-tiled pure-SIMT FMA reference (32x32 tile, shared-memory K chunks) computing the same fusion and route sm_110a / FLASHRT_FORCE_SIMT to it in torch_binding.cpp; sm_100/sm_103 keep the CUTLASS megakernel. Record the installed-artifact Thor validation (7/7 rows, cos>=0.99999976) and benchmark (85.6ms on M768,N16384,K2048, ~22x faster than the one-thread-per-output reference).
Add a pure-SIMT reference for the grouped NVFP4 block-scaled GEMM so the package is usable on sm_110a (Thor), where the CUTLASS SM120_16x8x64_TN_VS MMA atom asserts. The binding routes non-SM120 devices (and FLASHRT_FORCE_SIMT=1 diagnostics) to the SIMT path; SM120 keeps the native tiles. The correctness test now runs the full case matrix on both paths. build.toml gains a torch-only portable kernel entry with 11.0a capability. The source loader builds for the current device instead of hardcoding 12.0a. Add a benchmark CLI for the SIMT path.
The block-scaled mma path is SM120-only and asserts on sm_110a (Thor). Add a force_simt flag: the binding sets it when FLASHRT_FORCE_SIMT is set or the device major is 11, so every shape runs the portable SIMT reference on Thor while SM120 keeps the validated mma kernel.
The kernel uses Ampere-class mma.sync.aligned.m16n8k16 tensor cores, so it is not SM120-only. Declare 11.0a in build.toml, relax the hardware gate to SM100+ (the true Blackwell floor), and record the Thor validation (Torch 2.11 / CUDA 13.2, installed artifact).
Replace pytest-only imports with argparse CLIs that build the extension from package source (kernel-builder registration include) or load an installed artifact, covering the full case matrix on both backends. Fixes found during Thor verification: - fa2-seqused-runtime: include torch-ext/torch_binding.cpp in the source build (without it the module has no PyInit entry point). - flashrt-nvfp4/flashrt-fused-quant: source shims mirror the public wrapper validation (rows>0, dim divisible by 16) so rejection tests pass on both backends. - MiniMaxAI-msa-blackwell: pytest entrypoints share the module-loading globals via an autouse fixture instead of requiring script mode.
bf16-linear-gemv, flashrt-adarms-train, flashrt-qkv-epilogue-train, flashrt-rope-train, flashrt-siglip-fwd-fusion, flashrt-vocab-ce-train, fp8-prefill-attention-blackwell, linear-attention-seq-state. Each script supports --backend source|installed with kernel-call or region latency against eager/torch.compile baselines; RESULTS.md updates follow the benchmark runs.
Triton bundles a ptxas that rejects --gpu-name=sm_110a, breaking Triton JIT on Thor. Point Triton at the system CUDA 13.2 ptxas via TRITON_PTXAS_PATH or a symlink in the venv site-packages.
…fp8-ffn MLP gate - _load_source_ops hardcoded 12.0 for three packages, so the source sweep could not run on SM110 (Thor). Build for the current device capability. - The fp8_gelu_mlp_bf16 row gated against the independent torch-math reference with a fixed p99_abs<=1.0 bound. Abs error from fp8 rounding-order noise scales with output magnitude: at groot_vit the output p99 magnitude is ~3700 and the observed p99_abs is 1.125 (0.03% relative), so a fixed bound mis-calibrates large shapes. Gate the fused kernel bit-exact against the staged FlashRT ops (the package's authoritative migration-parity contract) and scale the torch-reference abs bound by the expected output magnitude.
Cap per-process CUDA memory (default 30 GB) in every package benchmark and demo runner so GPU-allocating kernels do not exhaust unified-memory hosts.
Handle already-aligned 2D frequency tensors without the unsqueeze loop and factor the per-tensor rotation into _rope_one.
… tests Convert the vocab-ce test to the standalone source/installed harness and let the grouped-moe source tests discover CUTLASS includes locally instead of requiring a fixed machine path.
Allow KERNEL_BUILDER_DOCKER to override the hardcoded builder path in the prebuild check and release build plan.
Document copied source files and local packaging edits per the source-sync convention.
Require CUTLASS_INCLUDE (or the package-specific env) instead of defaulting to /data/third_party or /home/heima checkout paths so the source-mode tests run on any Thor host. The runtime-demo test helper is also made overridable via KERNEL_BUILDER_REGISTRATION_INCLUDE.
Replace hardcoded /home/heima and /data checkout paths with env-overridable values and the repo's relative-sibling kernel-builder convention. Docs refer to <installed-dir> instead of a local artifact path.
Replace the pending-confirmation placeholder with the canonical repository git address where the packaged source is maintained.
Use <workspace> placeholders, PATH-resolved kernel-builder-docker, and repo-relative defaults in place of /home/heima and /workspace checkout paths.
…cap-and-sync-docs # Conflicts: # adaptive-layernorm-producers/SYNC.md # grouped-moe-gemm/VALIDATION.md # grouped-moe-gemm/benchmarks/benchmark.py # grouped-moe-gemm/tests/test_grouped_moe_gemm.py # grouped-moe-gemv/torch-ext/torch_binding.cpp
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Summary
Portable SIMT fallbacks and validation/benchmark hardening so the package set builds and runs on NVIDIA Thor (SM110) via the standard kernel-builder pipeline.
Highlights
Thor (SM110) support
fused-mlp-megakernels-blackwell: portable GeGLU SIMT fallback for SM110 (CUTLASS tcgen05 megakernel stays for SM100/SM103)grouped-moe-gemm: portable SIMT fallback section ([kernel.grouped_moe_gemm_portable], caps11.0a)grouped-moe-gemv: route SM11x devices to the portable SIMT kernelsageattention2-blackwell: add11.0acapabilityBenchmarks & tests
--max-mem-gbmemory guard on every package benchmark and demo CLI (default 30 GB)KERNEL_BUILDER_DOCKER/CUTLASS_INCLUDEenv overrides; machine-specific paths removed from test helpers and docsDocs
SYNC.mdprovenance notes for 7 packages referencing the flashrt-project repository<workspace>placeholders instead of machine pathsValidation