arc_ocd: Add Status32 halt bit check if jtag_status_ru=0 and target is running by EvgeniiDidin · Pull Request #33 · foss-for-synopsys-dwc-arc-processors/openocd

EvgeniiDidin · 2019-04-19T12:24:26Z

In rare cases ARC_JTAG_STAT_RU is set to 0, but STATUS32 halt bit is not "1". This
disparancy causes openocd to halt the processor. This patch
correctly handles sunch behaviour.

Signed-off-by: Evgeniy Didin didin@synopsys.com

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

>$ djtgcfg -d JtagHs2 prog -i 4 -f <fpga bit file to progam>.bit Signed-off-by: Frank Dols <frank.dols@synopsys.com>

particularly ARC-EM4 core registers r61 or r62 Signed-off-by: Frank Dols <frank.dols@synopsys.com>

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

…tion Signed-off-by: Frank Dols <frank.dols@synopsys.com>

…ss-for-synopsys-dwc-arc-processors/openocd.git into arc-0.7.0-dev-00151

Derived from tcl/interface/digilent-hs1.cfg. JTAG-HS3 has an open drain buffer on pin 14 for SRST to work with PS_SRST_B on Xilinx Zynq SoC. Change-Id: I1e9e72d0511528a61207e318aff937ae9fad5bf9 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/2728 Tested-by: jenkins Reviewed-by: Robert Jordens <jordens@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

Spotted by gcc: arm7_9_common.c: In function ‘arm7_9_unset_breakpoint’: arm7_9_common.c:353:4: error: this ‘if’ clause does not guard... [-Werror=misleading-indentation] if (current_instr == arm7_9->thumb_bkpt) ^~ arm7_9_common.c:356:5: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘if’ if (retval != ERROR_OK) ^~ The logic won't change once the braces have been added, as the new 'retval' check only makes sense within the if(). Change-Id: I6a303e118f2150e5eb25c9268ad06de5d8a533b2 Signed-off-by: Aleksander Morgado <aleksander@aleksander.es> Reviewed-on: http://openocd.zylin.com/3477 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>

It is identical to 2.2. Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>

Real version number of EM Starter Kit is 2.3, but documentation references 2.03a by mistake, which made its way into GNU products as well. Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>

As documented in openocd manual, 'reset run' command should reset the target and then let it run. There was an issue with that: after reset, target was not being run. This commit fixes this issue.

Configure files is regenerated because after previous commits they are not up to date.

Also, this patch splits invalidation/flushing of each cache on a separate functions.

The patch fixes a bug: when a writing to memory is needed, first of all, we should flush the cache, otherwise it may lead to data inconsistency.

…->state=running In rare cases ARC_JTAG_STAT_RU is set to 0, but STATUS32 halt bit is not "1". This disparancy causes openocd to halt the processor. This patch correctly handles sunch behaviour. Signed-off-by: Evgeniy Didin <didin@synopsys.com>

anthony-kolesov · 2019-05-20T19:42:08Z

Ough, I see now an email.

EvgeniiDidin · 2019-05-28T14:15:43Z

Hi @anthony-kolesov,

If everything is fine with updated commit, could you please apply it?
After that we could finally close the #30 issue.

anthony-kolesov · 2019-05-28T15:49:30Z

You should assign merge request to me, when you want me to review it again.

anthony-kolesov · 2019-05-28T15:54:04Z

Or, there is actually button to "Request review again".

anthony-kolesov · 2019-05-28T15:54:37Z

-			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+		/* In some cases JTAG status register indicates that
+		*  processor is in halt mode, but processor is still running.
+		*  We check halt bit of AUX STATUS32 register for setting correct state


Missing dot at the end of the sentence.

anthony-kolesov · 2019-05-28T15:56:40Z

+				target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+			}
+			else {
+				 LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, target is still running");


Missing dot at the end of the message, line is too long.

anthony-kolesov · 2019-05-28T15:57:43Z

+		*  We check halt bit of AUX STATUS32 register for setting correct state
+		*/
+		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
+			CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc32->jtag_info, AUX_STATUS32_REG, &value));


Line too long.

anthony-kolesov · 2019-05-28T15:59:51Z

-
-			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+		/* In some cases JTAG status register indicates that
+		*  processor is in halt mode, but processor is still running.


stars go under the star of the first line, not under the slash.

anthony-kolesov · 2019-05-28T16:00:29Z

+				CHECK_RETVAL(arc_dbg_debug_entry(target));
+				target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+			}
+			else {


Incorrect formatting of } and else.

The code of the function is based on: https://github.com/foss-for-synopsys-dwc-arc-processors/openocd/blob/master/src/target/arc_ocd.c#L49 Significant changes: * foss-for-synopsys-dwc-arc-processors#33 * Replaced arc_jtag_read_aux_reg_one() with high-level arc_get_register_value() Signed-off-by: Evgeniy Didin <didin@synopsys.com>

fdols added 30 commits November 17, 2014 17:18

ARC: core functions stack module interface

d85c972

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: debug functions stack module interface

0b71cca

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: arc700 OpenOCD interface

bd0f870

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: generic (arc32) functions stack module interface

7d0e61c

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: intro to all new modules

6d8b155

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: add monitor cmds to read/write core & aux regs

59c7374

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: mv openocd.cfg into tcl/target/snps_haps51_arc700.cfg

b42aebc

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: minor text update

cb21b87

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: remove not supported targets

7d286da

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: openocd.cfg for bottlenose and ml509

3ee5524

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: gettingstarted.txt on compiling and starting

ab8e4bf

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: (gdb)monitor arc read/write-mem-word

70a2cba

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: increase fastmem block size

96cb155

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: code cleanup on printf -> LOG_DEBUG/INFO/WARNING/USER

47889dd

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: info how to compile/run for developer versus customer

7c40369

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: move debug functions to the debug module

115c736

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: user manual update on telnet connectivity

e81612e

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: throw ARC700 out

141e58a

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: give us processor type switch support

543af81

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: reorganized content of getting started manual

cfb8a25

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: target configuration files incl. arc600

9a4887d

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: monitor arc set-core-into-halted + print-core-status

5d36de1

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: add arc600 support

67993ff

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: how to program FPGA with Digilent HS1 probe

faa44b0

>$ djtgcfg -d JtagHs2 prog -i 4 -f <fpga bit file to progam>.bit Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: prevent from reading/writing none existing core registers

986f72f

particularly ARC-EM4 core registers r61 or r62 Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: insert instruction cache flash on set_breakpoint

c7fa916

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: set proper CPUid for ARC700 on ML509

be177cb

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: build instruction how to build for Windows host

2dbad6f

Signed-off-by: Frank Dols <frank.dols@synopsys.com>

ARC: prevent from missing version.texi file when generating documenta…

a03471b

…tion Signed-off-by: Frank Dols <frank.dols@synopsys.com>

Merge branch 'claudiu-win_crosscompilation-mods' of git@github.com:fo…

13c4658

…ss-for-synopsys-dwc-arc-processors/openocd.git into arc-0.7.0-dev-00151

afaerber and others added 14 commits May 11, 2017 16:06

arc: Add config file for EM Starter Kit 2.03a

d0c80f1

It is identical to 2.2. Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>

arc: Add description for building and using OpenOCD on macOS

c332029

arc: Support HS Development Kit

790beb8

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>

Rename EM Starter Kit 2.03a to 2.3

ea4b323

Real version number of EM Starter Kit is 2.3, but documentation references 2.03a by mistake, which made its way into GNU products as well. Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>

arc: Added cJTAG support for ARC and FTDI interface

74f33f0

arc: Add EM Starter Kit 2.3 board file for cJTAG interface

80efacf

arc: Fix 'reset run' command for ARC.

8f8ce21

As documented in openocd manual, 'reset run' command should reset the target and then let it run. There was an issue with that: after reset, target was not being run. This commit fixes this issue.

arc: Mention support for ARC HSDK in readme

2057a7e

xxx: Add generated configure files

1372cc7

Configure files is regenerated because after previous commits they are not up to date.

arc: Add L2 cache support

1da07d3

Also, this patch splits invalidation/flushing of each cache on a separate functions.

arc: Add memory flushing to arc_mem_write_block32

6f45e23

The patch fixes a bug: when a writing to memory is needed, first of all, we should flush the cache, otherwise it may lead to data inconsistency.

arc: Add ARC IoT DevKit board sconfiguration file

72f0b9b

anthony-kolesov suggested changes Apr 19, 2019

View reviewed changes

Comment thread src/target/arc_ocd.c Outdated

Comment thread src/target/arc_ocd.c Outdated

Comment thread src/target/arc_ocd.c Outdated

Comment thread src/target/arc_ocd.c Outdated

Comment thread src/target/arc_ocd.c Outdated

anthony-kolesov mentioned this pull request Apr 19, 2019

GNU ARC toolchain debugging, constantly report error "Polling target arc700.cpu failed, GDB will be halted. Polling again in 100ms" #30

Closed

anthony-kolesov assigned EvgeniiDidin Apr 19, 2019

EvgeniiDidin force-pushed the master branch from 3a09674 to 76caa93 Compare May 16, 2019 13:02

anthony-kolesov self-assigned this May 28, 2019

anthony-kolesov self-requested a review May 28, 2019 15:53

anthony-kolesov suggested changes May 28, 2019

View reviewed changes

anthony-kolesov removed their assignment May 28, 2019

claziss force-pushed the master branch from 8ee31a5 to fc30feb Compare March 13, 2023 11:58

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

arc_ocd: Add Status32 halt bit check if jtag_status_ru=0 and target is running#33

arc_ocd: Add Status32 halt bit check if jtag_status_ru=0 and target is running#33
EvgeniiDidin wants to merge 285 commits into
foss-for-synopsys-dwc-arc-processors:masterfrom
EvgeniiDidin:master

EvgeniiDidin commented Apr 19, 2019

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

anthony-kolesov commented May 20, 2019

Uh oh!

EvgeniiDidin commented May 28, 2019

Uh oh!

anthony-kolesov commented May 28, 2019 •

edited

Loading

Uh oh!

anthony-kolesov commented May 28, 2019

Uh oh!

anthony-kolesov May 28, 2019

Uh oh!

anthony-kolesov May 28, 2019

Uh oh!

anthony-kolesov May 28, 2019

Uh oh!

anthony-kolesov May 28, 2019

Uh oh!

anthony-kolesov May 28, 2019

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

10 participants

Conversation

EvgeniiDidin commented Apr 19, 2019

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

anthony-kolesov commented May 20, 2019

Uh oh!

EvgeniiDidin commented May 28, 2019

Uh oh!

anthony-kolesov commented May 28, 2019 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

anthony-kolesov commented May 28, 2019

Uh oh!

anthony-kolesov May 28, 2019

Choose a reason for hiding this comment

Uh oh!

anthony-kolesov May 28, 2019

Choose a reason for hiding this comment

Uh oh!

anthony-kolesov May 28, 2019

Choose a reason for hiding this comment

Uh oh!

anthony-kolesov May 28, 2019

Choose a reason for hiding this comment

Uh oh!

anthony-kolesov May 28, 2019

Choose a reason for hiding this comment

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

10 participants

anthony-kolesov commented May 28, 2019 •

edited

Loading