hwpmc: Initial support for AMD IBS

[mashtizadeh]

This patch adds initial support for AMD IBS. It adds a new class of performance counter that cotains two events: ibs-fetch and ibs-op events. Unlike most existing sampled events, IBS events provide a number of values containing extra information regarding the sample. To support this we use the existing callchain event, and introduce a new flag for multipart payloads. The first 8 bytes of the pc_sample contains a header that defines up to four payloads.

Sponsored by: Netflix

[github-actions]

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[mashtizadeh]

I tested that I didn't break the i386 and aarch64 builds. On AMD64 I tested the existing AMD counters and the new IBS events using pmcstat.

I've made this patch a draft until I get an external consumer of the API to give me their approval, but otherwise it's ready for review. In addition, I plan to use the multipart payload to implement LBR/BRS. In the meantime, I'll cleanup and push my other diffs including documentation.

@bsdimp @mhorne

[mhorne]

Hi. I am unlikely to be able to review this in detail until next week.

I am not familiar with the AMD IBS feature. From a brief overview, it appears that it might be a better fit for the
hwt(4)/hwt(8) framework in FreeBSD. Have you looked into this? This tool is a divergence from hwpmc, added in the last few years to support tracing frameworks like ARM SPE and Intel PE.

Maybe or maybe it is not appropriate.

[mashtizadeh]

Yes I originally thought similarly, but the problem with IBS is that it needs to be used with specific counters to provide a complete picture. IBS is also not the only exception, BRS and LBR both make more sense using this approach as they will trigger off counters. For these reasons it was an early requirement from our downstream consumer of the hwpmc module.

[bsdimp]

where does 3 come from?

[mashtizadeh]

Needs to not collide with other AMD counters, the Intel counters are separate.

[bsdimp]

Just a couple of questions, but overall I think it looks good. Note: I've not verified the details match the docs on this, however.

[mashtizadeh]

Diff is ready. Took a little longer than expected to fix the stop logic once I hit this spurious NMI on one machine. Now the PMC stop consumes several steps to clear the counter, clear the enable bit, then retry in a loop to clear the entire control register for 50us.

[mashtizadeh]

Seems like someone broke kernel-toolchain so none of the builds are passing, nothing to do with hwpmc

[bsdimp]

So most of the failed builds are because monthly compute limit has been exceeded.