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30 changes: 30 additions & 0 deletions sys/dev/hwpmc/hwpmc_amd.c
Original file line number Diff line number Diff line change
Expand Up @@ -907,6 +907,36 @@
return (NULL);
}

/*
* Some PC vendors enable the core counters in firmware to track
* performance. The best guess is that this is being used to control
* power management from within the SMM mode. We shouldn't just take
* over the PMCs in this case. The user should try disabling any
* performance monitoring or power management functions in the BIOS to
* safely make use of the counters.
*/
for (i = 0; i < AMD_PMC_CORE_DEFAULT; i++) {

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Should these tests come after we have queried and set amd_core_npmcs? Or is it only important to check the first 6 counters?

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It's fine were it is, we should only see this on older machines. HWP and other mechanisms are providing alternative ways for them to continue to implement similar functionality without using the counters anymore. I can't repro it on any recent Intel or AMD machines I bought from those brands that I know have done this in the past.

Don't forget it needs to come above the VM check as that will touch the first PMC.

@mashtizadeh mashtizadeh Jun 12, 2026

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As for the helper function, I'll make that change and update this diff tomorrow or Saturday.

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I also owe you a patch to clean up the SYSTEM/USER flag it's going to work as you suggested, but I want to implement a best effort filtering. IBS isn't like other counters we get accurate samples but still suffer from skid during delivery.

if ((amd_feature2 & AMDID2_PCXC) != 0) {
error = rdmsr_safe(AMD_PMC_CORE_BASE + 2 * i, &reg);
} else {
if (i >= AMD_NPMCS_K8)
break;

error = rdmsr_safe(AMD_PMC_EVSEL_0 + i, &reg);
}

if (error != 0) {
printf("hwpmc: AMD evsel %d rdmsr failed!\n", i);
return (NULL);
}

if ((reg & AMD_PMC_ENABLE) != 0) {
printf("hwpmc: PMCs maybe in use by firmware!\n");
printf("hwpmc: Disable the PMC use in the BIOS before loading\n");

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return (NULL);
}
}

/*
* Unforunately, there is no way to communicate that the original four
* core counters are disabled through CPUIDs alone. We attempt to
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