Pull request for fix of SDA glitch#5
Conversation
1. Add default clause to FSMs in Bit
Controller and Byte Controller
2. Eliminate (for now) slave_reset from the
second master FSM reset clause
1. Eliminate unused reg slave_adr_received_d
in the bit controller since it depresses
the coverage score
2. Whitespace changes in states ST_SL_WAIT,
ST_SL_WR, and ST_SL_RD
3. Add reset to ST_IDLE upon slave_reset in
state ST_SL_WR
|
I think that the original intent of slave_reset in the In target reads, the final NACK on the bus indicates that it is time to recover, and the FSM uses it to return to In target writes, the FSM ends up in state If that's the case, the tb_i2c_herveille_oc testbench should to be extended to simulate unexpected STA/STO conditions. Anyway, the fix presented in this pull request gets the FSM out of state |
|
Thank you, @bobnewgard. I just spent an interesting hour concluding almost the same fix. I left the case statement as is and qualified |
|
I like your fix, since it seems to follow the spirit of the original code better than mine. My fix is limited to conditions uncovered by randomized transactions in the testbench so I cannot be sure that every reasonable case was covered. If it's possible to push your version to github, please do so. I'd like to see your fix in context. |
|
Thanks for the patch (gavin5342/i2c@44856f5). I will validate it in my testbench. If everything looks good, I will update this pull request. |
This pull request is associated with issue #4.
The changes in this pull request have been verified only in the testbench at https://codeberg.org/bobn/tb_i2c_herveille_oc. No hardware validation has been done.
The important change is to the
ST_SL_WRstate of the byte controllerc_stateFSM. Instead of resetting everything uponslave_reset, the change transitions the FSM toST_IDLEwhen the FSM is inST_SL_WRand slave_reset is high.I think that the addition of default clauses in FSM case statements is important in the presence of a single event upset (SEU). Of course, SEU mitigation only applies when targeting RAM-based FPGAs.
The FSM without a default clause would go into an indeterminate state, perhaps detectably, but perhaps not. With the default clause, the FSM halts, which is always detectable.
All whitespace changes are immaterial.